Brain-computer interfaces (BCIs) have the potential to revolutionize human-computer interaction and offer significant biomedical benefits by enabling applications such as closed-loop neuromodulation, mobility restoration for spinal cord injury patients, and therapies for neurodegenerative diseases. To fully leverage BCIs’ capabilities, it is crucial to enhance spatial resolution and robustness by increasing the number of recording channels and expanding brain area coverage. However, current approaches often focus on maximizing the channel count within a single recording analog front-end (AFE), limiting scalability and coverage.

This thesis introduces a novel architecture for a low-power and compact AFE, designed for seamless integration into a massively parallel array of distributed single-channel AFEs dedicated to micro-electrocorticography (μECoG) recording. The proposed AFE features a DC-coupled, chopper-stabilized low-noise boxcar sampler (LNB), followed by a passive switched-capacitor low-pass filter (SC-LPF) and a single-slope (SS) analog-to-digital converter (ADC). The LNB enhances anti-aliasing by introducing notches at multiples of the sampling frequency and effectively reduces chopping ripple. An 8-bit quantization is performed using a continuous time comparator synchronized with a globally distributed ramp across all channels of the array. The SS-ADC achieves a 12-bit resolution at the Nyquist rate (1 kSps) through oversampling at a rate of 16 times (OSR = 16).

Additionally, a novel electrode DC offset (EDO) cancellation loop prevents LNB saturation due to large EDO values, ensuring reliable performance in practical scenarios. Notably, this design eliminates the need for large AC coupling capacitors traditionally used for EDO cancellation, leading to a more compact design and improved scalability for high-density neural recording applications.

The proposed architecture is implemented at the transistor level in 40 nm CMOS technology and extensively validated through simulations. The AFE achieves exceptional area efficiency, with an estimated footprint of only 0.0028 mm² per channel. Moreover, the AFE achieves an input-referred noise (IRN) of 1.69 μV_rms over 0.5-500 Hz and provides an EDO compensation exceeding 100 mVpp. The design exhibits an input impedance of 71.4 MΩ and a common-mode rejection ratio (CMRR) of 80.94 dB. Additionally, the AFE achieves a signal-to-noise ratio (SNR) of 43.3 dB with a 1 mV_pp input signal. These results indicate that the presented AFE architecture, and specifically the novel compensation scheme, represent a promising approach for neural recording applications.

The recording of biosignals, such as atrial electrograms (AEG), electrocardiograms (ECG), and electroencephalograms (EEG), is progressing towards the adoption of more dense electrode arrays in order to improve spatial and temporal resolution. The proliferation of channels necessitates some form of channel sharing technique so that efficient low power and area recording can be achieved.
In this thesis, a code-division multiplexed analog front-end is designed due to its efficient use of bandwidth in comparison to time and frequency multiplexing. Orthogonal coding schemes such as Walsh-Hadamard sequences are best suited for minimising cross-talk. These codes are typically implemented using an LUT or processor which becomes a significant overhead when a large number of channels are to be multiplexed. However, by investigating the sequences closely, a novel method of generating these codes from a clock signal using digital logic was devised. The proposed algorithm to generate these sequences on-chip provides significant area savings for sequences of length greater than 8, which makes the design scalable for a large number of channels,. The reduction in area ranges from a factor of 10 for a code length of 8 up to a factor as large as 200 for a code length of 128.
As orthogonal sequences require a low bandwidth, a low bandwidth low-noise amplifier and ADC were used for amplification and digitisation of the signal. By using digitally inspired analog blocks, such as an inverter-based amplifier, lower power consumption could be achieved.
The entire design was implemented to share 7 channels. The code generator, low-noise amplifier and ADC consume a total of 78.4μW, which corresponds to 11.2μW per channel. This is a 3.3x improvement to the design in [5] where pseudo-random sequences were used as the coding scheme. However, the design consumes more power than a state-of-the-art design reported in [6] which uses 1.97μW per channel. While the design is currently not optimized with respect to power consumption in comparison to the design in [6], the novel code generation technique reported in this thesis makes the design scalable for larger number of channels. This is because the area constraint of the LUT is no more the limiting factor in terms of area.

Switched-capacitor power converters (SCPCs) have emerged as promising alternatives to traditional inductive power converters due to their CMOS integration capability and configurable conversion ratios. However, challenges such as output ripple, power efficiency, and transient response have hindered their widespread adoption. This article presents a novel Hybrid Hysteresis-CFM (HHC) control strategy that effectively addresses these issues.

The HHC strategy combines the best of both worlds, integrating hysteresis control and Continuous Frequency Modulation (CFM) control. During transient moments, the system utilizes a coarse/fine frequency tuning approach to rapidly reach the target frequency. Simultaneously, hysteresis control ensures that overshoot and undershoot are kept within predefined limits, significantly reducing output ripple during load transitions.

To enhance performance and versatility, the proposed system employs a Recursive Switched Capacitor (RSC) topology with adaptive capacitor sizing and 10-phase time-interleaving. This configuration enables configurable voltage-conversion ratios (VCRs) and high power conversion efficiency (PCE) across a wide input-output range.

Experimental results validate the effectiveness of the HHC SCPC. It demonstrates minimal overshoot and undershoot during load transition, maintains a low output voltage ripple during steady-state operation, and achieves high PCE. Comparative analysis with state-of-the-art DC-DC converters underscores the superior performance of the proposed system.

In summary, the Hybrid Hysteresis-CFM (HHC) control strategy offers a promising solution to enhance the capabilities of switched-capacitor power converters. Its ability to address output ripple, power efficiency, and transient response challenges makes it a valuable innovation for diverse applications requiring efficient power conversion.