DZ
D. Zhang
info
Please Note
<p>This page displays the records of the person named above and is not linked to a unique person identifier. This record may need to be merged to a profile.</p>
3 records found
1
Conference paper
(2014)
-
D Deligiannis, S Alizizatos, A Ingenito, D Zhang, M van Sebille, RACMM van Swaaij, M Zeman
A symmetric structure has been generally used to fabricate heterojunction with intrinsic thin layer (HIT) solar cells, i.e. hydrogenated amorphous silicon (a-Si:H) forms the emitter (i-p stack) and the back surface field (BSF) (i-n stack), and transparent conductive oxide (TCO) covered with metallic electrodes is used on either side. In this contribution, we present the influence of the intrinsic a-Si:H layer thickness in both the emitter and BSF on the passivation and solar-cell performance. Using a thicker intrinsic a-Si:H layer in the emitter results in a longer effective minority carrier lifetime, indicating a better passivation of the a-Si:H/c-Si interface and leading to a higher open-circuit voltage (Voc). In the BSF, thinner or even no intrinsic a-Si:H can be used to increase FF. In both the emitter and BSF, the fill factor (FF) is strongly related to the intrinsic a-Si:H layer thickness. In our investigation, the short circuit current density (Jsc) does not change obviously with the variation of the intrinsic a-Si:H layer thickness. In the case that a full metal contact is used on the BSF side, the solar cell without back TCO shows a better performance. An efficiency of 17.5% is obtained in the flat HIT solar cell without intrinsic a-Si:H passivating layer and TCO on the side of BSF.
...
A symmetric structure has been generally used to fabricate heterojunction with intrinsic thin layer (HIT) solar cells, i.e. hydrogenated amorphous silicon (a-Si:H) forms the emitter (i-p stack) and the back surface field (BSF) (i-n stack), and transparent conductive oxide (TCO) covered with metallic electrodes is used on either side. In this contribution, we present the influence of the intrinsic a-Si:H layer thickness in both the emitter and BSF on the passivation and solar-cell performance. Using a thicker intrinsic a-Si:H layer in the emitter results in a longer effective minority carrier lifetime, indicating a better passivation of the a-Si:H/c-Si interface and leading to a higher open-circuit voltage (Voc). In the BSF, thinner or even no intrinsic a-Si:H can be used to increase FF. In both the emitter and BSF, the fill factor (FF) is strongly related to the intrinsic a-Si:H layer thickness. In our investigation, the short circuit current density (Jsc) does not change obviously with the variation of the intrinsic a-Si:H layer thickness. In the case that a full metal contact is used on the BSF side, the solar cell without back TCO shows a better performance. An efficiency of 17.5% is obtained in the flat HIT solar cell without intrinsic a-Si:H passivating layer and TCO on the side of BSF.
Heterojunction silicon with intrinsic thin layer (HIT) solar cells that combine advanced thin-film hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si) technologies are promising because of the high performance at low cost. Due to the low conductivity of a-Si:H, indium tin oxide (ITO) needs to be used as a front contact layer on top of a-Si:H in order to collect photogenerated currents. The thin a-Si:H layer requires the ITO deposition to be soft so that the passivation is maintained after deposition. Otherwise, the passivation degradation resulting from ITO deposition should be recovered by some post processing. In this contribution, we investigate how the power density and the temperature during ITO deposition as well as post annealing influence the passivation quality of HIT solar cells as characterised by the open-circuit voltage (Voc) and minority carrier lifetime. Firstly, ITO sputtering with lower power density can reduce the degradation of the passivation quality after ITO deposition. Secondly, we have investigated the simultaneous annealing during ITO deposition at elevated temperature. On one hand, simultaneous annealing can recover some of the degradation resulting from sputtering. On the other hand, there is a temperature threshold above which degradation of the passivation is observed, probably by hydrogen effusion. Thirdly, we observe that post annealing can fully recover the degradation resulting from ITO sputtering at room temperature (RT).
...
Heterojunction silicon with intrinsic thin layer (HIT) solar cells that combine advanced thin-film hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si) technologies are promising because of the high performance at low cost. Due to the low conductivity of a-Si:H, indium tin oxide (ITO) needs to be used as a front contact layer on top of a-Si:H in order to collect photogenerated currents. The thin a-Si:H layer requires the ITO deposition to be soft so that the passivation is maintained after deposition. Otherwise, the passivation degradation resulting from ITO deposition should be recovered by some post processing. In this contribution, we investigate how the power density and the temperature during ITO deposition as well as post annealing influence the passivation quality of HIT solar cells as characterised by the open-circuit voltage (Voc) and minority carrier lifetime. Firstly, ITO sputtering with lower power density can reduce the degradation of the passivation quality after ITO deposition. Secondly, we have investigated the simultaneous annealing during ITO deposition at elevated temperature. On one hand, simultaneous annealing can recover some of the degradation resulting from sputtering. On the other hand, there is a temperature threshold above which degradation of the passivation is observed, probably by hydrogen effusion. Thirdly, we observe that post annealing can fully recover the degradation resulting from ITO sputtering at room temperature (RT).