L.P. Prielinger
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3 records found
1
Revisiting the Mapping of Quantum Circuits
Entering the Multi-core Era
When physical architectures become too complex for analytical study, numerical simulation proves essential to investigate quantum network behavior. Although highly informative, these simulations involve intricate numerical functions without known analytical forms, making traditional optimization techniques that assume continuity, differentiability, or convexity inapplicable. We introduce a more efficient computational framework that employs machine learning models as surrogates for the objective function. We demonstrate the effectiveness of our approach by applying it to three well-known optimization problems in quantum networking: allocating quantum memory across multiple nodes, tuning an experimental parameter in every physical link of a quantum entanglement switch, and finding effective protocol configurations in a large asymmetric quantum network. Our algorithm consistently outperforms Simulated Annealing and Bayesian optimization within the allotted time, improving results by up to 29% and 28%, respectively. Our framework will thus allow for more comprehensive quantum network studies, integrating surrogate-assisted optimization with existing quantum network simulators.
Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate.