Memristor-based Computation-In-Memory (CIM) architectures are a genre of emerging computing designs, and they have the potential to provide a power-efficient computational power for artificial intelligence (AI). However, current memristor-based CIM designs face the challenges from non-idealities, such as read disturb. The mitigation of non-idealities in CIM architectures is an area of active research.

Simulation tools are important design tools for CIM. Conventionally, SPICE simulations are used for CIM architectures. Modern high-level simulation frameworks for CIM are faster when compared to SPICE, and therefore it is desirable to investigate the feasibility of non-ideality analysis, such as read disturb analysis, in high-level simulations. However, current high-level simulators do not include a model for read disturb, and they are not suitable for read disturb analysis.

To fill this gap, this thesis presents RdaCIM, a read-disturb-aware CIM simulator. RdaCIM is high-level simulation tool that exploits parallelism provided by multi-core CPUs and AVX instructions. More importantly, RdaCIM involves the non-trivial non-ideality of read disturb into the simulations, which makes it possible for the user to perform read disturb related investigations on the simulator.

Experiments have been done with RdaCIM to show the feasibility of read disturb analysis on this tool. The effectiveness of a rewriting scheme as a countermeasure to read disturb is verified on RdaCIM. Furthermore, an effort to reduce the overhead of rewriting by dynamic voltage adjustment is presented and verified with RdaCIM. Performance benchmarks have been done to elaborate the benefits of the parallelised implementation of the simulation tool. ... Read more