This BSc Thesis is about the construction and control elements of the airplane group of the Solar Drone project. The project aims to improve the flight time of aerial vehicles, using solar energy. This document is delves into the possibility of applying solar cells to small model aircrafts. It outlines the challenges and solutions involved in building and controlling such a system. A ready-available airframe and fitting components will be used, in combination with a custom photo-voltaic and energy system, to create a prototype. The prototype takes the form of an unmanned aerial vehicle, making it capable of extended flights without requiring extensive monitoring. It will serve as a testing platform for the performance of the PV modifications done to the aircraft. Included in this document are simulations for calculating optimal solar panel placement inside a transparent wing with opaque ribs, in addition to software and hardware modifications that were required to make the other systems work well in combination with the custom energy system.

In spite of progress on hardware design languages, the design of high-performance hardware accelerators forces many design decisions specializing the interfaces of these accelerators in ways that complicate the understanding of the design and hinder modularity and collaboration. In response to this challenge, Tydi has been presented as an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. Earlier efforts in providing an implementation framework for Tydi managed to generate VHDL boilerplate code for Tydi interfaces, but offered limited design value over custom solutions due to VHDL's low abstraction level. In contrast, Chisel, with its high level of abstraction and customizability offers a suitable platform to implement Tydi-based components. In this thesis, the Tydi-Chisel library is presented along with an A-to-Z design-process description for data-streaming accelerators. A stream-interface solution is presented that offers both compatibility with Tydi in traditional HDLs and maximum utility within Chisel through two intercompatible representations. In addition, design complexity is reduced through novel utilities like stream-complexity conversion, developed to alleviate interface specification mismatches between components. Using the presented toolchain and library, the amount of code required to specify Tydi interfaces for representative use-cases can be reduced several times compared to a Verilog description, while offering increased utility. Tydi-Chisel aims to simplify the design of data-streaming accelerators through the integration of the Tydi interface standard in Chisel, along with helper components, syntax sugar, and verification tools. In combination Chisel and Tydi help bridge the hardware-software divide, making solo-design and collaboration between designers easier.