Technology Aware Network-on-Chip Connectivity and Synchronization Design

Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture

Mesochronous NoC Technology for Power-Efficient GALS MPSoCs

Topology exploration

A library of dual-clock FIFOs for cost-effective and flexible MPSoCs design

The synchronization challenge

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

Architecture design principles for the integration of synchronization interfaces into network-on-chip switches

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

Designing regular network-on-chip topologies under technology, architecture and software constraints

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

SARC power estimation methodology

Performance analysis of RR and FQ algorithms in reconfigurable routers