In this paper, we present a fully integrated RFDAC-based outphasing power amplifier (ROPA) in 40-nm CMOS that achieves 22.2 dBm peak output power with 49.2% drain efficiency at 5.9 GHz. It employs differential quasi-load-insensitive Class-E branch PAs that can dynamically be segmented using a 3-bit digital amplitude control word to improve efficiency at power back-off. At 8 dB back-off, this segmentation technique improves the ROPA drain and system efficiency by 5% and 7%, respectively, when compared to a non-segmented approach.

High-voltage CMOS drivers can boost performance in base-station RF power amplifiers (PA). Base-station RF PAs are realized in dedicated transistor technologies like Si LDMOS or GaN HEMT while digital/baseband/lower-power blocks are done in Si CMOS. The PA technologies in base stations normally require high-voltage swings (e.g. 5V) for their optimum input drive.
This thesis investigates two approaches for implementing high-voltage (HV) CMOS drivers for such transistors in low-breakdown voltage baseline CMOS technology, in particular TSMC 65-nm CMOS.
As a first approach, cascoding topologies are investigated. Class E has been used to preserve efficiency. The main efficiency loss mechanisms have been identified and two topologies are proposed: 3 and 4 stacked devices. Only standard devices have been used in this approach to facilitate re-use in other deep sub-micron CMOS technologies. More than 5.5 and 7.0V output swings have been reached with the 3 and 4 stacked devices topologies, respectively. The complexity increases and the efficiency reduces with the number of stacked devices. Deep N-Wells and dedicated biasing networks are needed for the 4-device cascode topology. However, recently other HV solutions employing special extended-drain (ED) devices have outperformed the best results of this cascode approach, showing than the use of those ED devices is advantageous for high-voltage/power applications.
A second approach consisted in exploring an inverter-based topology, employing special ED devices recently available in the baseline 65-nm CMOS technology. Three CMOS drivers were designed, implemented and fabricated. CMOS drivers I and II employed novel thin-oxide ED devices, while CMOS driver III used thick-oxide ED devices. Additionally, pre-driver stages with standard thin-oxide devices were implemented in the CMOS driver I. The three CMOS drivers demonstrated the feasibility of a complete broadband and high-efficiency amplifier lineup bridging the gap between GaN and CMOS technologies. CMOS driver I reached the best performance due to its pre-drivers. The use of thick-gate oxide, in CMOS driver III, was found not to be optimum for the application due to its required high input power. Additionally, in view of the application, the drivers had duty-cycle control capabilities to enhance efficiency. The CMOS driver I reached a duty-cycle range of 32 to 70% with a 5pF load, within a 2.1 to 2.7GHz bandwidth.