YZ
Y. Zhang
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With the continuous scaling of integrated circuits, the current density in interconnect lines increases sharply, making electromigration (EM) a critical factor limiting device reliability. As a potential alternative to copper (Cu) and aluminum (Al) interconnects, cobalt (Co) has gradually attracted research attention. However, studies and experimental verification of EM in Co interconnects remain incomplete.
In this study, a systematic investigation of electromigration in Co interconnect structures was carried out through both simulation and experimental approaches. For the simulation part, a 3D finite element model consisting of a Co interconnect layer, TiN barrier layer, SiO₂ isolation layer, and Si substrate was developed on the COMSOL Multiphysics platform, leveraging its powerful multiphysics modeling and coupled analysis capabilities. Electro-thermal-mechanical-diffusion coupling was performed to obtain multiphysics results, including temperature distribution, current density vector field, thermal stress distribution, and atomic concentration evolution. The main driving forces for the formation of electromigration-induced hillocks and voids were analyzed accordingly.
For the experimental part, Co layers were fabricated using sputtering combined with wet etching, as well as e-beam evaporation combined with a lift-off process. Accelerated lifetime tests were conducted under high current density and elevated temperature conditions, and SEM was employed to characterize failure morphology. The results indicate that for the Co test structures fabricated by sputtering combined with wet etching, a significant increase in resistance was observed under a current density of 1.0× 10¹⁰ A/m^2 (30mA) and a temperature of 300 °C. However, no distinct electromigration-induced morphological changes were detected under SEM. Even when the current density was increased further, no obvious hillock or void formation was observed. Only when the current density was raised to 1.3× 10¹⁰ A/m^2 (40mA) did catastrophic melting occur in the Co layer. For the evaporated and lift-off Co structures, no definitive EM-related morphological changes were observed either.
In conclusion, no effective EM phenomena were observed experimentally, and the results did not align with the simulations. This discrepancy is possibly due to limitations in the quality of the fabricated test samples. Future work should focus on optimizing fabrication methods and processes, and employing more diverse characterization techniques to provide stronger evidence for identifying electromigration-induced failure in cobalt interconnects.
Keywords: electromigration, cobalt, simulation, fabrication, interconnects. ...
In this study, a systematic investigation of electromigration in Co interconnect structures was carried out through both simulation and experimental approaches. For the simulation part, a 3D finite element model consisting of a Co interconnect layer, TiN barrier layer, SiO₂ isolation layer, and Si substrate was developed on the COMSOL Multiphysics platform, leveraging its powerful multiphysics modeling and coupled analysis capabilities. Electro-thermal-mechanical-diffusion coupling was performed to obtain multiphysics results, including temperature distribution, current density vector field, thermal stress distribution, and atomic concentration evolution. The main driving forces for the formation of electromigration-induced hillocks and voids were analyzed accordingly.
For the experimental part, Co layers were fabricated using sputtering combined with wet etching, as well as e-beam evaporation combined with a lift-off process. Accelerated lifetime tests were conducted under high current density and elevated temperature conditions, and SEM was employed to characterize failure morphology. The results indicate that for the Co test structures fabricated by sputtering combined with wet etching, a significant increase in resistance was observed under a current density of 1.0× 10¹⁰ A/m^2 (30mA) and a temperature of 300 °C. However, no distinct electromigration-induced morphological changes were detected under SEM. Even when the current density was increased further, no obvious hillock or void formation was observed. Only when the current density was raised to 1.3× 10¹⁰ A/m^2 (40mA) did catastrophic melting occur in the Co layer. For the evaporated and lift-off Co structures, no definitive EM-related morphological changes were observed either.
In conclusion, no effective EM phenomena were observed experimentally, and the results did not align with the simulations. This discrepancy is possibly due to limitations in the quality of the fabricated test samples. Future work should focus on optimizing fabrication methods and processes, and employing more diverse characterization techniques to provide stronger evidence for identifying electromigration-induced failure in cobalt interconnects.
Keywords: electromigration, cobalt, simulation, fabrication, interconnects. ...
With the continuous scaling of integrated circuits, the current density in interconnect lines increases sharply, making electromigration (EM) a critical factor limiting device reliability. As a potential alternative to copper (Cu) and aluminum (Al) interconnects, cobalt (Co) has gradually attracted research attention. However, studies and experimental verification of EM in Co interconnects remain incomplete.
In this study, a systematic investigation of electromigration in Co interconnect structures was carried out through both simulation and experimental approaches. For the simulation part, a 3D finite element model consisting of a Co interconnect layer, TiN barrier layer, SiO₂ isolation layer, and Si substrate was developed on the COMSOL Multiphysics platform, leveraging its powerful multiphysics modeling and coupled analysis capabilities. Electro-thermal-mechanical-diffusion coupling was performed to obtain multiphysics results, including temperature distribution, current density vector field, thermal stress distribution, and atomic concentration evolution. The main driving forces for the formation of electromigration-induced hillocks and voids were analyzed accordingly.
For the experimental part, Co layers were fabricated using sputtering combined with wet etching, as well as e-beam evaporation combined with a lift-off process. Accelerated lifetime tests were conducted under high current density and elevated temperature conditions, and SEM was employed to characterize failure morphology. The results indicate that for the Co test structures fabricated by sputtering combined with wet etching, a significant increase in resistance was observed under a current density of 1.0× 10¹⁰ A/m^2 (30mA) and a temperature of 300 °C. However, no distinct electromigration-induced morphological changes were detected under SEM. Even when the current density was increased further, no obvious hillock or void formation was observed. Only when the current density was raised to 1.3× 10¹⁰ A/m^2 (40mA) did catastrophic melting occur in the Co layer. For the evaporated and lift-off Co structures, no definitive EM-related morphological changes were observed either.
In conclusion, no effective EM phenomena were observed experimentally, and the results did not align with the simulations. This discrepancy is possibly due to limitations in the quality of the fabricated test samples. Future work should focus on optimizing fabrication methods and processes, and employing more diverse characterization techniques to provide stronger evidence for identifying electromigration-induced failure in cobalt interconnects.
Keywords: electromigration, cobalt, simulation, fabrication, interconnects.
In this study, a systematic investigation of electromigration in Co interconnect structures was carried out through both simulation and experimental approaches. For the simulation part, a 3D finite element model consisting of a Co interconnect layer, TiN barrier layer, SiO₂ isolation layer, and Si substrate was developed on the COMSOL Multiphysics platform, leveraging its powerful multiphysics modeling and coupled analysis capabilities. Electro-thermal-mechanical-diffusion coupling was performed to obtain multiphysics results, including temperature distribution, current density vector field, thermal stress distribution, and atomic concentration evolution. The main driving forces for the formation of electromigration-induced hillocks and voids were analyzed accordingly.
For the experimental part, Co layers were fabricated using sputtering combined with wet etching, as well as e-beam evaporation combined with a lift-off process. Accelerated lifetime tests were conducted under high current density and elevated temperature conditions, and SEM was employed to characterize failure morphology. The results indicate that for the Co test structures fabricated by sputtering combined with wet etching, a significant increase in resistance was observed under a current density of 1.0× 10¹⁰ A/m^2 (30mA) and a temperature of 300 °C. However, no distinct electromigration-induced morphological changes were detected under SEM. Even when the current density was increased further, no obvious hillock or void formation was observed. Only when the current density was raised to 1.3× 10¹⁰ A/m^2 (40mA) did catastrophic melting occur in the Co layer. For the evaporated and lift-off Co structures, no definitive EM-related morphological changes were observed either.
In conclusion, no effective EM phenomena were observed experimentally, and the results did not align with the simulations. This discrepancy is possibly due to limitations in the quality of the fabricated test samples. Future work should focus on optimizing fabrication methods and processes, and employing more diverse characterization techniques to provide stronger evidence for identifying electromigration-induced failure in cobalt interconnects.
Keywords: electromigration, cobalt, simulation, fabrication, interconnects.
To extend Moore’s law, silicon carbide devices attend the researcher’s attention due to their irreplaceable advantages such as high critical breakdown electrical field, wide bandgap and excellent thermal conductivity without sacrificing too much charge carrier mobility. However, the defects on the SiC-oxide interface degrades the performance of the device and even get worse at high temperature, such as the threshold voltage shifting problems, limiting the design of the integrated circuits. The thesis models, characterise, analyses, measures and extracts the traps of SiC MOSCAP, to understand the trapped charge transportation and unreliability mechanism under high temperature.
Effectively using SiC materials necessitates the need to understand the physical properties itself. Due to the large bandgap, the inversion layer cannot be observable in low frequency C-V measurement. The electrical field, space charge region, surface potential and C-V curve in SiC devices all differ from Si devices. More importantly, the trapped charges fluctuate the surface potential of the SiC devices. To give insight into the mechanism governing the trapped charges, the mathematical solution of the trapped charges in the whole bandgap is solved.
To be specific, the trap behaviour at a single energy level is then followed. A nonzero transient current is generated due only to the capture and release of the trapped charges when the equilibrium condition is broken. The trapped charges with high energy are thermalized and an equivalent admittance is obtained which further be split into a capacitance and a conductance.
Rising temperature activates the dopant atoms that are not ionised, and the Fermi level shifts towards the midband. The variation of equivalent circuit components and physical parameters responds to the temperature. High temperature expands the SiC crystal and the trapped charges are easy to receive energy from phonons so that the interaction between traps and the conduction band is enhanced and more empty states are waiting for the recombination of the charge carriers. ...
Effectively using SiC materials necessitates the need to understand the physical properties itself. Due to the large bandgap, the inversion layer cannot be observable in low frequency C-V measurement. The electrical field, space charge region, surface potential and C-V curve in SiC devices all differ from Si devices. More importantly, the trapped charges fluctuate the surface potential of the SiC devices. To give insight into the mechanism governing the trapped charges, the mathematical solution of the trapped charges in the whole bandgap is solved.
To be specific, the trap behaviour at a single energy level is then followed. A nonzero transient current is generated due only to the capture and release of the trapped charges when the equilibrium condition is broken. The trapped charges with high energy are thermalized and an equivalent admittance is obtained which further be split into a capacitance and a conductance.
Rising temperature activates the dopant atoms that are not ionised, and the Fermi level shifts towards the midband. The variation of equivalent circuit components and physical parameters responds to the temperature. High temperature expands the SiC crystal and the trapped charges are easy to receive energy from phonons so that the interaction between traps and the conduction band is enhanced and more empty states are waiting for the recombination of the charge carriers. ...
To extend Moore’s law, silicon carbide devices attend the researcher’s attention due to their irreplaceable advantages such as high critical breakdown electrical field, wide bandgap and excellent thermal conductivity without sacrificing too much charge carrier mobility. However, the defects on the SiC-oxide interface degrades the performance of the device and even get worse at high temperature, such as the threshold voltage shifting problems, limiting the design of the integrated circuits. The thesis models, characterise, analyses, measures and extracts the traps of SiC MOSCAP, to understand the trapped charge transportation and unreliability mechanism under high temperature.
Effectively using SiC materials necessitates the need to understand the physical properties itself. Due to the large bandgap, the inversion layer cannot be observable in low frequency C-V measurement. The electrical field, space charge region, surface potential and C-V curve in SiC devices all differ from Si devices. More importantly, the trapped charges fluctuate the surface potential of the SiC devices. To give insight into the mechanism governing the trapped charges, the mathematical solution of the trapped charges in the whole bandgap is solved.
To be specific, the trap behaviour at a single energy level is then followed. A nonzero transient current is generated due only to the capture and release of the trapped charges when the equilibrium condition is broken. The trapped charges with high energy are thermalized and an equivalent admittance is obtained which further be split into a capacitance and a conductance.
Rising temperature activates the dopant atoms that are not ionised, and the Fermi level shifts towards the midband. The variation of equivalent circuit components and physical parameters responds to the temperature. High temperature expands the SiC crystal and the trapped charges are easy to receive energy from phonons so that the interaction between traps and the conduction band is enhanced and more empty states are waiting for the recombination of the charge carriers.
Effectively using SiC materials necessitates the need to understand the physical properties itself. Due to the large bandgap, the inversion layer cannot be observable in low frequency C-V measurement. The electrical field, space charge region, surface potential and C-V curve in SiC devices all differ from Si devices. More importantly, the trapped charges fluctuate the surface potential of the SiC devices. To give insight into the mechanism governing the trapped charges, the mathematical solution of the trapped charges in the whole bandgap is solved.
To be specific, the trap behaviour at a single energy level is then followed. A nonzero transient current is generated due only to the capture and release of the trapped charges when the equilibrium condition is broken. The trapped charges with high energy are thermalized and an equivalent admittance is obtained which further be split into a capacitance and a conductance.
Rising temperature activates the dopant atoms that are not ionised, and the Fermi level shifts towards the midband. The variation of equivalent circuit components and physical parameters responds to the temperature. High temperature expands the SiC crystal and the trapped charges are easy to receive energy from phonons so that the interaction between traps and the conduction band is enhanced and more empty states are waiting for the recombination of the charge carriers.