Experimental Analysis and Circuit-Level Mitigation Strategies for Intermittent Errors in Resistive RAMs

Abstract

Resistive RAM (RRAM) design optimization and error monitoring is crucial for memory storage applications but also to enable future brain-inspired systems beyond the capabilities of today’s hardware. The figure-of-merit confirming the presence of resistive switching in RRAM devices is its resistance window expressed by the HRS/LRS ratio (High Resistance State over the Low Resistance State). This ratio guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell becomes in storing and retrieving data. From this perspective, this paper proposes an analysis of RRAM intermittent errors with respect to the RRAM resistance ratio. The impact of intermittent errors on the HRS/LRS ratio is analyzed at the RRAM cell electrical level using a dedicated test chip. Silicon measurements show that all detected RRAM intermittent errors directly result from resistance drifts due to ineffective programming operations. In view of these findings, intermittent error mitigation schemes are proposed to address these errors at the circuit level.