A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur
Jiang Gong (TU Delft - OLD QCD/Charbon Lab)
F. Sebasatiano (TU Delft - (OLD)Applied Quantum Architectures)
E Charbon-Iwasaki-Charbon (Intel Corporation, École Polytechnique Fédérale de Lausanne)
Masoud Babaie (TU Delft - Electronics)
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Abstract
This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.