Fault Tolerant Design for Memristor-based AI Accelerators
T. Spyrou (TU Delft - Computer Engineering)
A. Zografou (TU Delft - Electrical Engineering, Mathematics and Computer Science)
S. Hamdioui (TU Delft - Computer Engineering)
A. Gebregiorgis (TU Delft - Computer Engineering)
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Abstract
Computation-In-Memory (CIM) using emerging memristive devices offers a promising solution to implementing energy efficient Artificial Intelligence (AI) hardware accelerators. Though, the non-idealities characterizing memristive devices cause a negative impact on the performance of CIM-based micro-architectures. We propose a two-step fault tolerance strategy to address the impact of Stack-at Faults (SAFs) and conductance variation of RRAM crossbar arrays, composed of a fault tolerant activation function and a retraining method. Evaluation results on Binary Neural Network (BNNs) architectures trained with MNIST, Fashion-MNIST, and CIFAR-10 datasets demonstrate that the proposed techniques can restore the classification accuracy by up to 20%, 40% and 80%, respectively.