Wafer-level direct bonding of optimized superconducting NbN for 3D chip integration

Journal Article (2021)
Author(s)

Ye Li (Student TU Delft)

Amir Mirza Mirza Gheytaghi (TU Delft - Electronic Components, Technology and Materials)

M Trifunovic (TU Delft - QID/Ishihara Lab)

Yuanxing Xu (Student TU Delft)

Guo Qi Zhang (TU Delft - Electronic Components, Technology and Materials)

R Ishihara (TU Delft - QID/Ishihara Lab, Kavli institute of nanoscience Delft, TU Delft - Quantum Circuit Architectures and Technology)

Research Group
Electronic Components, Technology and Materials
Copyright
© 2021 Ye Li, Amir Mirza Gheytaghi, M. Trifunovic, Yuanxing Xu, Kouchi Zhang, R. Ishihara
DOI related publication
https://doi.org/10.1016/j.physc.2021.1353823
More Info
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Publication Year
2021
Language
English
Copyright
© 2021 Ye Li, Amir Mirza Gheytaghi, M. Trifunovic, Yuanxing Xu, Kouchi Zhang, R. Ishihara
Research Group
Electronic Components, Technology and Materials
Volume number
582
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Abstract

3D integration has well-developed for traditional CMOS technology operating at room temperature, but few studies have been performed for cryogenic applications such as quantum computers. In this paper, a wafer-to-wafer bonding of superconductive joints based on niobium nitride (NbN) is performed to demonstrate the possibility of 3D integration of superconducting chips. The NbN thin films are deposited by magnetron sputtering. Its high critical temperature (15.2 K) is achieved by optimizing the sputtering recipe in terms of N2 flow rate and discharge voltage. Wafer-level bumping is bonded by the thermo-compression method. The sheet resistance of the thin film and the contact resistance of the joints are measured by the Greek-cross (4-point Kelvin method) and daisy chain structures at cryogenic temperature, respectively. Direct-bonding wafers with NbN superconductive joints avoid using adhesive layers and the bonding interface could still present superconducting electrical connections in a cryogenic environment above 4 K, which will allow us to use a smaller and high-cooling power cryostat. The contribution of this work could lead to the fabrication of multi-layered superconducting chip that operates beneficially in cryogenic temperature, which is essential in building scalable quantum processors.