M. Trifunovic
Please Note
8 records found
1
3D integration has well-developed for traditional CMOS technology operating at room temperature, but few studies have been performed for cryogenic applications such as quantum computers. In this paper, a wafer-to-wafer bonding of superconductive joints based on niobium nitride (NbN) is performed to demonstrate the possibility of 3D integration of superconducting chips. The NbN thin films are deposited by magnetron sputtering. Its high critical temperature (15.2 K) is achieved by optimizing the sputtering recipe in terms of N2 flow rate and discharge voltage. Wafer-level bumping is bonded by the thermo-compression method. The sheet resistance of the thin film and the contact resistance of the joints are measured by the Greek-cross (4-point Kelvin method) and daisy chain structures at cryogenic temperature, respectively. Direct-bonding wafers with NbN superconductive joints avoid using adhesive layers and the bonding interface could still present superconducting electrical connections in a cryogenic environment above 4 K, which will allow us to use a smaller and high-cooling power cryostat. The contribution of this work could lead to the fabrication of multi-layered superconducting chip that operates beneficially in cryogenic temperature, which is essential in building scalable quantum processors.
Solution-processing has gained widespread attention over the past years due to their potential low-cost advantage in terms of fabrication of electronics as well as application to flexible electronics. Cyclopentasilane is used for the solution-based processing of silicon. As a liquid, the material has the potential to be applied directly on low-cost flexible substrates that generally have a low thermal budget, by annealing the liquid using an excimer laser treatment. So far, electronics based on this material have only been demonstrated on rigid and high cost substrates. In this work, silicon has been applied as a solution on top of a paper substrate and processed into PMOS and NMOS thin-film transistors (TFTs). The maximum fabrication temperature was limited to approximately 100° C. By being able to fabricate devices on top of a paper substrate, a pathway opens towards new applications that combine the true low-cost and biodegradability with the high performance of silicon electronics.