Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture
Sumit Diware (TU Delft - Computer Engineering)
Anteneh Gebregiorgis (TU Delft - Computer Engineering)
Rajiv V. Joshi (IBM Research)
Said Hamdioui (TU Delft - Quantum & Computer Engineering)
Rajendra Bishnoi (TU Delft - Computer Engineering)
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Abstract
Emerging memristor-based computing has the potential to achieve higher computational efficiency over conventional architectures. Bit-slicing scheme, which represents a single neural weight using multiple memristive devices, is usually introduced in memristor-based neural networks to meet high bit-precision demands. However, the accuracy of such networks can be significantly degraded due to non-zero minimum conductance $(\mathrm{G}_{min})$ of memristive devices. This paper proposes an unbalanced bit-slicing scheme; it uses smaller slice sizes for more important bits to provide higher sensing margin and reduces the impact of non-zero $\mathrm{G}_{min}$. Moreover, the unbalanced bit-slicing is assisted by 2’s complement arithmetic which further improves the accuracy. Simulation results show that our proposed scheme can achieve up to $8.8 \times $ and $1.8 \times $ accuracy compared to state-of-the-art for single-bit and two-bit configurations respectively, at reasonable energy overheads.