Cryo-CMOS Integrator-Based DAC for Scalable Biasing of Semiconductor Qubits

Abstract

Semiconductor-based cryogenic quantum processors require the accurate biasing of a large number of gate electrodes, which are typically individually wired to room-temperature DACs. To prevent the wiring bottleneck when scaling to future very large processors, this work proposes a scalable cryo-CMOS DAC that can operate with a S&H demultiplexer close to the quantum processor. By adopting an integrator-based switched-capacitor DAC with a dynamically-biased high-voltage output stage, both the required large output range and high resolution can be achieved while sharing the DAC over a large number of electrodes, thus improving the power efficiency. Fabricated in a 22-nm FinFET technology, the DAC occupies 0.076 mm2. At 4.2 K (RT), it achieves an LSB of 57.1 µV (68.3 µV) over a 3 V range with 188 µVrms (192µVrms) noise and 36.5-LSB (12.6-LSB) INL while dissipating 157 µW (138 µW). The low power dissipation and the potential to drive more than 30,000 electrodes paves the way for scalable biasing of quantum processors operating down to mK temperatures.