Single-grain Si TFTs with ECR-PECVD gate SiO2

Journal article (2004)

Authors

R. Ishihara Electronic Components, Technology and Materials - EEMCS
Y Hiroshima External organisation
D Abe External organisation
BD van Dijk Electronic Components, Technology and Materials - EEMCS
PC van der Wilt Electronic Components, Technology and Materials - EEMCS
S Higashi External organisation
S Inoue External organisation
T Shimoda External organisation
JW Metselaar Electronic Components, Technology and Materials - EEMCS
C.I.M. Beenakker Electronic Components, Technology and Materials - EEMCS
Research Group
Electronic Components, Technology and Materials (EEMCS) (TU Delft)
More Info
expand_more

Published Date

2004

Language

Undefined/Unknown

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Components, Technology and Materials

Abstract

High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.