Single-grain Si TFTs with ECR-PECVD gate SiO2

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Single-grain Si TFTs with ECR-PECVD gate SiO2

Journal Article (2004)

Author(s)

R. Ishihara (TU Delft - Electronic Components, Technology and Materials)

Y Hiroshima (External organisation)

D Abe (External organisation)

BD van Dijk (TU Delft - Electronic Components, Technology and Materials)

PC van der Wilt (TU Delft - Electronic Components, Technology and Materials)

S Higashi (External organisation)

S Inoue (External organisation)

T Shimoda (External organisation)

JW Metselaar (TU Delft - Electronic Components, Technology and Materials)

CIM Beenakker (TU Delft - Electronic Components, Technology and Materials)

Research Group

Electronic Components, Technology and Materials

Academic journal papers ZX CWTS 1.00 <= JFIS < 3.00

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https://resolver.tudelft.nl/uuid:b696c73b-4538-4eb1-9b32-af09a0a957dd

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Publication Year

2004

Research Group

Electronic Components, Technology and Materials

Issue number

3

Volume number

51

Pages (from-to)

500-502

Abstract

High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.

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