Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach

Conference paper (2004)

Authors

P Celinski Microelectronics
S Al-Sarawi External organisation
D Abbott External organisation
S.D. Cotofana Computer Engineering - EEMCS
S Vassiliadis Computer Engineering - EEMCS
Department
Microelectronics
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Published Date

2004

Language

Undefined/Unknown

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Department

Microelectronics