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D Abbott
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7 records found
Delay evaluation of high speed data-path circuits based on threshold logic
Conference paper -
P Celinski
,
D Abbott
,
S.D. Cotofana
A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder
Conference paper -
P Celinski
,
S.D. Cotofana
,
D Abbott
State-of-the-art in CMOS threshold-logic VSLI gate implementations and applications
Conference paper -
P Celinski
,
S.D. Cotofana
,
JF López
,
S Al-Sarawi
,
D Abbott
Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach
Conference paper -
P Celinski
,
S Al-Sarawi
,
D Abbott
,
S.D. Cotofana
,
S Vassiliadis
Threshold logic parallel counters for 32-bit multipliers
Conference paper -
P Celinski
,
S.D. Cotofana
,
D Abbott
Area efficient, High speed parallel counter circuits using charge recycling threshold logic
Conference paper -
P Celinski
,
D Abbott
,
S.D. Cotofana
Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates
Conference paper -
P Celinski
,
S.D. Cotofana
,
D Abbott