Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

Conference paper (2019)

Authors

L. Wu Computer Engineering - EEMCS , IMEC
G. Cardoso Medeiros Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
S. Couet IMEC
S. Hamdioui Quantum & Computer Engineering
Research Group
Computer Engineering (EEMCS) (TU Delft)
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Published Date

2019

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

The STT-MRAM manufacturing process involves not only traditional CMOS process steps, but also the integration of magnetic tunnel junction (MTJ) devices, the data-storing elements. This paper demonstrates a paradigm shift in fault modeling for STT-MRAMs by performing defect modeling and fault analysis for MTJ pinhole defects which are seen as a key type of STT-MRAM manufacturing defects. A Verilog-A compact model for defect-free MTJ devices is built and calibrated with electrical measurements on actual MTJ wafers. MTJs with a pinhole defect are extensively characterized, both during manufacturing test (t=0) and in the field (t>0), and the data is used to extend our defect-free MTJ compact model to include parameterized pinhole defects. The model is then used to perform single-cell static fault analysis and this shows not only what
kind of faults can occur in an STT-MRAM, but also that the conventional fault modeling approach based on linear resistors cannot catch such behavior.

Files

ETS19.pdf
(.pdf | 1.18 Mb)