Ultra-Low-Noise Cryogenic Multilevel Memristors for Sub-100 μV Spin Qubit Biasing

Conference Paper (2025)
Author(s)

Erbing Hua (TU Delft - Quantum Circuit Architectures and Technology, TU Delft - Computer Engineering)

Stijn Heemskerk (Student TU Delft)

Nikolaj Nitzsche (TU Delft - Quantum Circuit Architectures and Technology)

Wagno Braganca (TU Delft - QID/Ishihara Lab, TU Delft - QuTech Advanced Research Centre)

Hanzhi Xun (TU Delft - Computer Engineering)

Ali Kaichouhi (TU Delft - Support Quantum Engineering)

Ryoichi Ishihara (TU Delft - QID/Ishihara Lab, TU Delft - Quantum Circuit Architectures and Technology, TU Delft - QuTech Advanced Research Centre)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.1109/IEDM50572.2025.11353526 Final published version
More Info
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Publication Year
2025
Language
English
Research Group
Computer Engineering
Publisher
IEEE
ISBN (print)
979-8-3315-6786-6
ISBN (electronic)
979-8-3315-6785-9
Event
2025 IEEE International Electron Devices Meeting, IEDM 2025 (2025-12-06 - 2025-12-10), San Francisco, United States
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Abstract

We demonstrate interface-enhanced memristors (OxReRAM) tailored for cryogenic spin-qubit control. By engineering a sparse filament network, our devices achieve eight nonvolatile resistance levels with an ultra-low read noise rate of around 0.3 %. When embedded in a cryogenic gain stage with RL = 30 kΩ and Vin = 0.3 V, it will deliver a ±1 V output range and sub-100-μV resolution using only six memristors per channel. This single-line biasing architecture will reduce wires, paving the way for large-scalce quantum processors.

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