Reinforcement bipolar read: addressing read disturb in RRAM

Abstract

Memory advances have not kept up with computing demands. Emerging device technology Resistive RAM (RRAM) addresses this by enabling computation-in-memory. However, RRAM suffers from read disturb, limiting viability. While earlier work has had some success in reducing read disturb by switching the read current direction (a bipolar read scheme), the RRAM device eventually degraded. In this work, a reinforcing bipolar read scheme is introduced, which aims to prevent read disturb by reinforcing both HRS and LRS, away from the undefined state. From device-level simulation, this reinforcing behaviour is predicted for V = 0.5, 0.4 and 0.3 V with a fixed switching ratio between time under positive and negative read voltage polarity rsw i tch = 2.5, 2.5 and 2.75, respectively. At V = 0.2 V and V = 0.1 V, it is predicted that no reinforcement scheme exists. The bipolar read scheme found for V = 0.5 V was evaluated in circuit simulation with a sense amplifier. however the HRS and LRS reinforcing behaviour found at device-level could not be replicated. From unipolar read results at circuit level, it was determined no switching ratio exists that reinforces both the HRS and LRS state boundaries as chosen here at RHRS,min = 12.8kΩ and RLRS,max = 4.4kΩ for V = 0.5 V. However, a 5.1x reduction in resistance drift compared to conventional unipolar read was still obtained.