Print Email Facebook Twitter A System-Level Aging and Mitigation Assessment Simulation Framework Title A System-Level Aging and Mitigation Assessment Simulation Framework Author Jeyachandra, Evelyn Rashmi (TU Delft Electrical Engineering, Mathematics and Computer Science; TU Delft Microelectronics) Contributor van Leuken, T.G.R.M. (mentor) Zjajo, Amir (mentor) de Graaf, A.C. (graduation committee) Kumar, S.S. (graduation committee) Hamdioui, S. (graduation committee) van der Meijs, N.P. (graduation committee) Degree granting institution Delft University of Technology Programme Electrical Engineering | Embedded Systems Date 2017-07-12 Abstract As technology scaling enters the nanometer regime, device aging effects cause quality and reliability issues in CMOS Integrated Circuits (ICs), which in turn shorten its lifetime. Evaluating system aging through circuit simulations is very complex and time consuming. In this thesis, a framework is proposed, which allows for the evaluation of long-term aging effects of ICs and the corresponding measures to counteract premature failure. The focus of this work lies in the abstraction of low-level aging models to system-level models, in order to facilitate swift high-level simulation, without any knowledge of underlying circuit dynamics. Two major aging mechanisms, namely Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) degradation are considered for analysis. System-level aging management is performed with the prototype of a System-on-Chip (SoC) including a Management Unit (MU), which counteracts aging by employing Dynamic Voltage Scaling (DVS), Dynamic Frequency Scaling (DFS), and Adaptive Body Biasing (ABB). The simulation platform prototype is based on System-C AMS and a 65-nm technology library. This SoC simulation computes path delay using characterized models, which represent the aged behaviour of individual circuit elements. Results show that the obtained values are within 2% of circuit-level simulation values at the cost of a simulation time which is 15x lesser than conventional circuit simulators (e.g. Cadence NCSim). Subject System-level agingIC lifetimeNBTICHCDynamic voltage scalingDynamic frequency scalingAdaptive Body Bias To reference this document use: http://resolver.tudelft.nl/uuid:9c942c1b-58be-42f0-accf-0bbe0947b208 Part of collection Student theses Document type master thesis Rights © 2017 Evelyn Rashmi Jeyachandra Files PDF Thesis_Evelyn_Rashmi_Jeya ... handra.pdf 1.83 MB Close viewer /islandora/object/uuid:9c942c1b-58be-42f0-accf-0bbe0947b208/datastream/OBJ/view