Print Email Facebook Twitter A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation Title A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation Author Chen, Wei (Fudan University) Jiang, Jing (Fudan University) Meda, Abdulmelik H. (The Hong Kong Polytechnic University) Ibrahim, Mesfin S. (Ctr. for Adv. Research in Photonics) Zhang, Kouchi (TU Delft Electronic Components, Technology and Materials) Fan, J. (Fudan University) Date 2023 Abstract SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wire-bonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of $8\times {8} \times {0}.{75}$ mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The experimental results revealed that: 1) SiC MOSFET FOPLP had 0.36 nH drain-source parasitic inductance at 100 kHz, a 96% reduction compared with a conventional wire-bonded package; 2) double-sided cooling enabled the packages to exhibit a thermal resistance as low as 0.55 °C/W; and 3) after 2000 thermal cycling cycles, drain-source ON-state resistance [RDS(on)] increased by less than 2%, which revealed the higher reliability of the package under thermal cycling. Subject CopperFan-out panel-level packaging (FOPLP)InductanceMOSFETPackagingparasitic inductanceReliabilitySiC MOSFETSilicon carbidethermal cyclingThermal resistancethermal resistance To reference this document use: http://resolver.tudelft.nl/uuid:ffe0d3aa-2796-45a5-9440-e87d86fb6b15 DOI https://doi.org/10.1109/TED.2023.3263150 Embargo date 2023-10-16 ISSN 0018-9383 Source IEEE Transactions on Electron Devices, 70 (5), 2268-2275 Bibliographical note Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. Part of collection Institutional Repository Document type journal article Rights © 2023 Wei Chen, Jing Jiang, Abdulmelik H. Meda, Mesfin S. Ibrahim, Kouchi Zhang, J. Fan Files PDF A_Thin_and_Low_Inductance ... uation.pdf 2.55 MB Close viewer /islandora/object/uuid:ffe0d3aa-2796-45a5-9440-e87d86fb6b15/datastream/OBJ/view