Thermomechanical Oriented Reliability Enhancement of Si MOSFET Panel-Level Packaging Fusing Ant Colony Optimization With Backpropagation Neural Network

Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a fan-out panel-level packaging (FOPLP) design for 30-V Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). To achieve...

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities...

High-temperature nanoindentation characterization of sintered nano-copper particles used in high power electronics packaging

Nano-copper sintering is one of new die-attachment and interconnection solutions to realize the wide bandgap semiconductor power electronics packaging with benefits on high temperature, low inductance, low thermal resistance and low cost. Aiming to assess the high-temperature reliability of sintered nano-copper die-attachment and...

Random voids generation and effect of thermal shock load on mechanical reliability of light-emitting diode flip chip solder joints

To make the light-emitting diode (LED) more compact and effective, the flip chip solder joint is recommended in LED chip-scale packaging (CSP) with critical functions in mechanical support, heat dissipation, and electrical conductivity. However, the generation of voids always challenges the mechanical strength, thermal stability, and...