RB
R.P.M. Bakker
info
Please Note
<p>This page displays the records of the person named above and is not linked to a unique person identifier. This record may need to be merged to a profile.</p>
2 records found
1
Information exchange through the countless webservices is central in the current age of technology, which increases the importance for security in these developments. One such security feature is the validation of data based on standardized data structures. The aim of this thesis is to develop a flexible hardware-accelerated text-based recognizer that provides this strict syntax validation.
To this end, a parsing machine architecture was adopted in order to fulfill the flexibility and strict recognition requirements. The parsing machine architecture was developed by formalizing the fundamental PEG expressions and creating a micro-architecture based on these PEG expressions, which led to the specification of the PPEG instruction set architecture. This architecture was then mathematically formalized and a proof for its strict adherence to the formalized PEG behavior was provided. The parsing machine architecture was implemented on an FPGA, a virtualization of the parsing machine was implemented in Python for easy analysis of its behavior, and a PEG compiler and assembler were developed for the PEG-PPEG translation. Finally, a memoization unit was developed as an extension to the parsing machine for an improved parsing throughput.
By running benchmarks for CSV, XML, JSON, and Java files on the PPEG parsing machine implementation, its parsing behavior was analyzed and compared to existing solutions. This showed that the minimum stack sizes depend solely on the size and complexity of the PEG; the percentage of clock cycles spent on jumps in instruction and data memory is substantial, ranging from 18\% and 40\%; the PPEG-compiled binary code size is relatively small compared to other solutions; and the throughput of the PPEG parsing machine is comparable if not better than other solutions running on faster hardware. Finally, the memoization unit was found to benefit large complex grammars more than small grammars.
...
To this end, a parsing machine architecture was adopted in order to fulfill the flexibility and strict recognition requirements. The parsing machine architecture was developed by formalizing the fundamental PEG expressions and creating a micro-architecture based on these PEG expressions, which led to the specification of the PPEG instruction set architecture. This architecture was then mathematically formalized and a proof for its strict adherence to the formalized PEG behavior was provided. The parsing machine architecture was implemented on an FPGA, a virtualization of the parsing machine was implemented in Python for easy analysis of its behavior, and a PEG compiler and assembler were developed for the PEG-PPEG translation. Finally, a memoization unit was developed as an extension to the parsing machine for an improved parsing throughput.
By running benchmarks for CSV, XML, JSON, and Java files on the PPEG parsing machine implementation, its parsing behavior was analyzed and compared to existing solutions. This showed that the minimum stack sizes depend solely on the size and complexity of the PEG; the percentage of clock cycles spent on jumps in instruction and data memory is substantial, ranging from 18\% and 40\%; the PPEG-compiled binary code size is relatively small compared to other solutions; and the throughput of the PPEG parsing machine is comparable if not better than other solutions running on faster hardware. Finally, the memoization unit was found to benefit large complex grammars more than small grammars.
...
Information exchange through the countless webservices is central in the current age of technology, which increases the importance for security in these developments. One such security feature is the validation of data based on standardized data structures. The aim of this thesis is to develop a flexible hardware-accelerated text-based recognizer that provides this strict syntax validation.
To this end, a parsing machine architecture was adopted in order to fulfill the flexibility and strict recognition requirements. The parsing machine architecture was developed by formalizing the fundamental PEG expressions and creating a micro-architecture based on these PEG expressions, which led to the specification of the PPEG instruction set architecture. This architecture was then mathematically formalized and a proof for its strict adherence to the formalized PEG behavior was provided. The parsing machine architecture was implemented on an FPGA, a virtualization of the parsing machine was implemented in Python for easy analysis of its behavior, and a PEG compiler and assembler were developed for the PEG-PPEG translation. Finally, a memoization unit was developed as an extension to the parsing machine for an improved parsing throughput.
By running benchmarks for CSV, XML, JSON, and Java files on the PPEG parsing machine implementation, its parsing behavior was analyzed and compared to existing solutions. This showed that the minimum stack sizes depend solely on the size and complexity of the PEG; the percentage of clock cycles spent on jumps in instruction and data memory is substantial, ranging from 18\% and 40\%; the PPEG-compiled binary code size is relatively small compared to other solutions; and the throughput of the PPEG parsing machine is comparable if not better than other solutions running on faster hardware. Finally, the memoization unit was found to benefit large complex grammars more than small grammars.
To this end, a parsing machine architecture was adopted in order to fulfill the flexibility and strict recognition requirements. The parsing machine architecture was developed by formalizing the fundamental PEG expressions and creating a micro-architecture based on these PEG expressions, which led to the specification of the PPEG instruction set architecture. This architecture was then mathematically formalized and a proof for its strict adherence to the formalized PEG behavior was provided. The parsing machine architecture was implemented on an FPGA, a virtualization of the parsing machine was implemented in Python for easy analysis of its behavior, and a PEG compiler and assembler were developed for the PEG-PPEG translation. Finally, a memoization unit was developed as an extension to the parsing machine for an improved parsing throughput.
By running benchmarks for CSV, XML, JSON, and Java files on the PPEG parsing machine implementation, its parsing behavior was analyzed and compared to existing solutions. This showed that the minimum stack sizes depend solely on the size and complexity of the PEG; the percentage of clock cycles spent on jumps in instruction and data memory is substantial, ranging from 18\% and 40\%; the PPEG-compiled binary code size is relatively small compared to other solutions; and the throughput of the PPEG parsing machine is comparable if not better than other solutions running on faster hardware. Finally, the memoization unit was found to benefit large complex grammars more than small grammars.
SPPE: Smart Personal Protective Equipment
UVGI Group
Bachelor thesis
(2020)
-
R.P.M. Bakker, M.J.H. Brouwers, H.W. van Zeijl, W.D. van Driel, S.D. Cotofana
The Smart Personal Protective Equipment (SPPE) is proposed as a result of the COVID-19 pandemic, which has led to shortages of standard face masks. This thesis describes one of the three subsystems of the SPPE, namely the Ultraviolet Germicidal Irradiation (UVGI). The UVGI subsystem provides the SPPE with an in situ disinfection system, in order to prolong the period in which the filters of the SPPE can be used to at least 8 hours. The UVGI is implemented by the use of UV LEDs. This implementation is done in two steps. Step one is a simulation which allows for the optimization of the LED placement depending on a multitude of parameters, including: distance between the LEDs and the filter, and the LED tilt angle. The second step is the design of a driver circuit, to allow for the adjustment of the dose applied by the LEDs. The simulation resulted in an LED array which offers the most optimal irradiation of the filter surface. The driver circuit has been designed, simulated to verify its functionality, and implemented in the form of a PCB design. The UVGI subsystem provides the SPPE with an in situ disinfection system by delivering a base dose of 305 mJ/cm2 and a driver circuit which allows for adjusting this dose, should this be desired. The UVGI subsystem should be able to extend the period in which the filters of the SPPE can be used to at least 8 hours. However, due to the restriction of not being allowed to create a prototype this has not yet been verified.
...
The Smart Personal Protective Equipment (SPPE) is proposed as a result of the COVID-19 pandemic, which has led to shortages of standard face masks. This thesis describes one of the three subsystems of the SPPE, namely the Ultraviolet Germicidal Irradiation (UVGI). The UVGI subsystem provides the SPPE with an in situ disinfection system, in order to prolong the period in which the filters of the SPPE can be used to at least 8 hours. The UVGI is implemented by the use of UV LEDs. This implementation is done in two steps. Step one is a simulation which allows for the optimization of the LED placement depending on a multitude of parameters, including: distance between the LEDs and the filter, and the LED tilt angle. The second step is the design of a driver circuit, to allow for the adjustment of the dose applied by the LEDs. The simulation resulted in an LED array which offers the most optimal irradiation of the filter surface. The driver circuit has been designed, simulated to verify its functionality, and implemented in the form of a PCB design. The UVGI subsystem provides the SPPE with an in situ disinfection system by delivering a base dose of 305 mJ/cm2 and a driver circuit which allows for adjusting this dose, should this be desired. The UVGI subsystem should be able to extend the period in which the filters of the SPPE can be used to at least 8 hours. However, due to the restriction of not being allowed to create a prototype this has not yet been verified.