In this paper, the effect of thermal stress on the reliability of the gate dielectric layer of SiC MOSFET at high short-circuit temperature is studied. By modeling and simulation, different shapes and materials (SiO2, BPSG, Si3N4) of the dielectric layer were compared regarding t
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In this paper, the effect of thermal stress on the reliability of the gate dielectric layer of SiC MOSFET at high short-circuit temperature is studied. By modeling and simulation, different shapes and materials (SiO2, BPSG, Si3N4) of the dielectric layer were compared regarding their stress distribution effects. Results indicate that elliptical gate structures and dual-layer ILD configurations perform better under thermal stress than conventional designs, particularly with Si3N4 as the inner layer and BPSG as the outer layer. This optimization scheme aims to enhance the reliability of SiC MOSFETs.
