In this paper, the effect of thermal stress on the reliability of the gate dielectric layer of SiC MOSFET at high short-circuit temperature is studied. By modeling and simulation, different shapes and materials (SiO2, BPSG, Si3N4) of the dielectric layer were compared regarding their stress distribution effects. Results indicate that elliptical gate structures and dual-layer ILD configurations perform better under thermal stress than conventional designs, particularly with Si3N4 as the inner layer and BPSG as the outer layer. This optimization scheme aims to enhance the reliability of SiC MOSFETs.

In this article, the avalanche withstand capability and transient failure model of commercial 1200 V asymmetric trench gate SiC MOSFETs are investigated by experiment and simulation under single-pulse unclamped inductive switching (UIS) conditions. The limiting avalanche current and limiting avalanche energy of the device are determined by evaluating the voltage and current waveforms, the power dissipation, and the avalanche energy curves before and during avalanche failure. Then, by using the calibrated simulation model, the sequence between the critical electric field stress and critical thermal stress suffered by the device is revealed, and the transient failure mode of the device is proved to be the thermal runaway. Moreover, after decapping the failed device, the failure mode of the device is further confirmed by analyzing the failure point. Finally, by using the focused ion beam (FIB) technology, the failure mechanism of the device is confirmed as a structural rupture caused by avalanche thermal stress.