The PEA(pulsed electro-acoustic) method is widely used for measuring space charge distribution in insulation materials. However, the measured quantity reflects a voltage curve over time rather than the actual space charge distribution. Therefore, establishing a calibration procedure is crucial to determine the relationship between these two quantities. This calibration procedure aims to convert the measured voltage into the spatial distribution of space charge while correcting for non-idealities such as distortion and attenuation. This paper outlines the main steps of the PEA system calibration and provides a detailed discussion on the selection of the reference signal. Furthermore, recommendations are provided to enhance the accuracy and reliability of the calibration process.

High-end power conversion applications increasingly use insulated metal substrate (IMS) printed circuit boards (PCBs) with very thin dielectrics to improve thermal performance. To ensure the reliability of these PCBs when exposed to high-frequency voltages, the breakdown and aging mechanisms of the PCB laminates under high-frequency voltage stress must be understood. This article investigates the breakdown and lifetime of these laminates using two high-frequency test sources for sinusoidal and square-wave voltages in the typical frequency range of 25–100 kHz and a test voltage up to 8 kV, which is a significant increase compared with the existing literature. Diagnostic tests, such as partial discharge (PD) measurement and dielectric frequency response analysis, are performed to analyze the high-frequency aging mechanisms further. Despite the rapid degradation of the insulation system under high-frequency voltage stresses, the results show that the IMS PCB laminates are quite robust, with high breakdown fields. The lifetime of the PCB laminates is found to vary approximately with the inverse of the frequency. Surface degradation due to the high inhomogeneous fields at the edges of the conducting planes is identified as one of the main lifetime risks. This is similar to more conventional PCB constructions. Diagnostic tests suggest that the accelerated degradation is due to highly localized PD activity and electrical treeing.

Innovative test methods are required to keep up with the increased demand for insulation materials which can withstand the high-frequency square-wave voltages generated by power-electronic equipment. Test systems using high-voltage, high-frequency transformers have proven versatile and easy to realise. The authors investigate the application of amorphous cut cores in such transformers. Analytical and numerical models for the transformer and its frequency response are developed, aiding the design process. An amorphous core-based transformer is designed for 8 kV_pk output at 100 kHz and compared to two previous designs based on ferrite cores. The frequency and pulse response, as well as the high-voltage and thermal performance, are evaluated. The comparison shows that while the low parasitics of the amorphous-based transformer allow for superior frequency response, they are unsuitable for long-duration tests with high pulse repetition frequencies (25–100 kHz) due to increased core losses. The partial discharge inception and flashover voltage are comparable to the ferrite-based transformers.

This paper comprehensively reviews several techniques that address the static and dynamic voltage balancing of series-connected MOSFETs. The effectiveness of these techniques was validated through simulations and experiments. Dynamic voltage-balancing techniques include gate signal delay adjustment methods, passive snubbers, passive clamping circuits, and hybrid solutions. Based on the experimental results, the advantages and disadvantages of each technique are investigated. Combining the gate-balancing core method with an RC snubber, which has proven both technically and commercially attractive, provides a robust solution. If the components are sorted and binned, voltage-balancing techniques may not be necessary, further enhancing the commercial viability of series-connected MOSFETs. An investigation of gate driver topologies yields one crucial conclusion: magnetically isolated gate drivers offer a simple and cost-effective solution for high-frequency (HF) applications (2.5–50 kHz) above 8 kV with an increased number of series devices. Below 8 kV, it is advantageous to move the isolation barrier from the gate drive IC to an optocoupler and isolated supply, allowing for a simple design with commercially available components.

As the integration of renewable energy sources into the grid increases, the insulation systems of grid components such as transformers and switchgear encounter significant challenges due to the transients and harmonics generated by power-electronic-based converters. A test generator capable of replicating these component stresses is essential to accurately evaluate these insulation systems under real-grid conditions. This paper proposes a modular cascaded H-bridge-based high-voltage arbitrary waveform generator, prototyped with three stages to generate customized waveforms (triangular, sawtooth, pulse, and complex) up to 8 kV. The H-bridge modules are designed using Si MOSFETs with a maximum blocking voltage of 4.5 kV. The input to the HV H-bridge module is provided by a 10 kV medium-frequency transformer, whose design is described with a focus on the insulation system and winding configuration. This transformer is driven by a zero-voltage switching driver. This arbitrary waveform generator excels in several aspects, including a straightforward design procedure, compact size, high voltage capability, ease of integration, and cost.