Superconducting nanowire single-photon detectors (SNSPDs) have emerged as leading cryogenic photon detectors, thanks to their high detection efficiency and low jitter. However, their large-scale integration remains limited by the wiring bottleneck between the cryogenic detectors and their room-temperature readout electronics. In applications such as color-center-based quantum computers (QCs), thousands of detectors may need to operate in parallel within a limited cryogenic cooling budget, thus asking for a scalable, low-power cryogenic electronic readout. To address these needs, this work introduces a cryogenic readout circuit directly wire-bonded to the SNSPD and using a high-impedance input to maximize the quality of the detector signal, thus relaxing the requirement of the cascaded amplifier and reducing its power consumption. An active quenching circuit is then adopted to ensure a reliable reset after the latching of the detector induced by such high input impedance. Implemented in 40-nm CMOS with an active area of <0.14 mm², the system achieves competitive performance at 0.1 K, delivering low timing jitter (<40 ps), high speed (dead time of ≈5 ns), and dark count rates (DCRs) below 1 Hz, while achieving a 5× reduction in power consumption (down to 20 μW) with respect to the cryogenic-readout state-of-the-art. Its ultralow-power operation and compact footprint make the proposed solution well-suited for integration within large-scale quantum-computing architectures.