This paper presents a scalable cryogenic readout solution for Superconducting Nanowire Single-Photon Detectors (SNSPDs) tailored for the readout of color-center-based qubits. The readout circuit, wire-bonded directly to the SNSPD, utilizes high input impedance to boost the signal amplitude, hence reducing the power consumption, and active quenching to prevent the latching induced by the high impedance. Fabricated in 40-nm CMOS in a 0.14-mm ² active area, the proposed system demonstrates competitive performance at 0.1 K, featuring low jitter [<60 ps Full Width at Half Maximum (FWHM)], high speed (dead time ≈ 5 ns) and low dark count rate (<1 Hz), while dissipating only 20 μ W. Such an ultra-low power and compact area enables the readout integration within a large-scale colorcenter quantum computer.

Micro-transfer printing (uTP) facilitates the integration of pre-characterized components from different substrates onto one common carrier die, enabling high-yield processes. Its highly parallel nature allows for exceptional throughput [1]. uTP has been successfully applied to III-V amplifiers, lasers [2], and quantum dot emitters [3], among others.

Micro-transfer printing (uTP) facilitates the integration of pre-characterized components from different substrates onto one common carrier die. Its highly parallel nature allows for exceptional throughput [1]. Up to now, uTP has been successfully applied to print III-V amplifiers, lasers [2] , and quantum dot emitters [3] , among others. Our research focuses on fabricating devices containing waveguide-integrated superconducting nanowire single-photon detectors (SNSPDs) [4], that are ready to be transferred. Thanks to their outstanding performance, SNSPDs integrated on low-loss Silicon Nitride waveguides enable optical quantum computing [5] and quantum key distribution [6]. Enabling the transfer of SNSPDs would allow for precise on-demand detector placement and circumvents fabrication constraints that could compromise the quality of the superconducting film.
The fabrication process involves the patterning nanowires, half-etched Si₃N₄ waveguides, and metal electrodes via electron beam lithography (EBL), followed by reactive ion etching (RIE), physical vapor deposition (PVD) or sputtering. In order for the Si₃N₄ device to be transferred, the final step employs hydrofluoric acid etching to dissolve the SiO₂ layer (see Fig. 1a and b) and make the device freestanding. Thereafter, a PDMS stamp is used to pick up the device, breaking its support structures and accurately place them on the dedicated carrier substrate.
This photonic architecture is optimized for detecting photons at a 930 nm wavelength. For sacrificial test devices, grating couplers at both ends of the suspended structures facilitate integrity and functionality testing during fabrication, while metal contacts to the SNSPDs allow for electrical pretesting. This approach allows for a precise placement of pre-characterized waveguide-integrated SNSPDs on any substrate and thus the creation of hybrid architectures necessary for fully on-chip quantum photonic applications.