Silicon carbide (SiC) devices have shown definite advantages over Si counterparts in high-temperature, high-voltage, and high-frequency applications. To fully exploit the potentiality of SiC devices in high temperatures, die-attach materials that can withstand high temperatures for a long time are required in the power electronics packaging. In this article, the high-temperature die-attach materials, such as high-temperature solders and transient liquid-phase bonding materials, were reviewed first. Then, metallic (mainly Ag and Cu) nanoparticles (NPs) sintering technologies were thoroughly overviewed. The metallic NPs sintering materials, metallic NPs sintering process, and interface and reliability were analyzed, respectively. Finally, the challenges and outlook of promising Cu NPs sintering technology were discussed.

SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.

In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermo-mechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.