Min Chen
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6 records found
1
The quantification of the extent and dynamics of land-use changes is a key metric employed to assess the progress toward several Sustainable Development Goals (SDGs) that form part of the United Nations 2030 Sustainable Development Agenda. In terms of anthropogenic factors threatening the conservation of heritage properties, such a metric aids in the assessment of achievements toward heritage sustainability solving the problem of insufficient data availability. Therefore, in this study, 589 cultural World Heritage List (WHL) properties from 115 countries were analyzed, encompassing globally distributed and statistically significant samples of “monuments and groups of buildings” (73.2%), “sites” (19.3%), and “cultural landscapes” (7.5%). Land-cover changes in the WHL properties between 2015 and 2020 were automatically extracted from big data collections of high-resolution satellite imagery accessed via Google Earth Engine using intelligent remote sensing classification. Sustainability indexes (SIs) were estimated for the protection zones of each property, and the results were employed, for the first time, to assess the progress of each country toward SDG Target 11.4. Despite the apparent advances in SIs (10.4%), most countries either exhibited steady (20.0%) or declining (69.6%) SIs due to limited cultural investigations and enhanced negative anthropogenic disturbances. This study confirms that land-cover changes are among serious threats for heritage conservation, with heritage in some countries wherein the need to address this threat is most crucial, and the proposed spatiotemporal monitoring approach is recommended.
In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermo-mechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.
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