The cardiac interpulse interval (IPI) has recently been proposed tofacilitate key exchange for implantable medical devices (IMDs) using apatient's own heartbeats as a source of trust. While this form of key exchangeholds promise for IMD security, its feasibility is not fully understood due tothe simplified approaches found in related works. For example, previouslyproposed protocols have been designed without considering the limitedrandomness available per IPI, or have overlooked aspects pertinent to arealistic system, such as imperfect heartbeat detection or the energy overheadsimposed on an IMD. In this paper, we propose a new IPI-based key-exchangeprotocol and evaluate its use during medical emergencies. Our protocol employsfuzzy commitment to tolerate the expected disparity between IPIs obtained by anexternal reader and an IMD, as well as a novel way of tackling heartbeatmisdetection through IPI classification. Using our protocol, the expected timefor securely exchanging an 80-bit key with high probability (1-10−6) is roughlyone minute, while consuming only 88 μJ from an IMD.

A promising alternative for treating absence seizures has emerged through closed-loop neurostimulation, which utilizes a wearable or implantable device to detect and subsequently suppress epileptic seizures. Such devices should detect seizures fast and with high accuracy, while respecting the strict energy budget on which they operate. Previous work has overlooked one or more of these requirements, resulting in solutions which are not suitable for continuous closed-loop stimulation. In this paper, we perform an in-depth design space exploration of a novel seizure-detection algorithm, which uses a complex Morlet wavelet filter and a static thresholding mechanism to detect absence seizures. We consider both the accuracy and speed of our detection algorithm, as well as various trade-offs with device autonomy when executed on a low-power processor. For example, we demonstrate that a minimal decrease in average detection rate of only 1.83% (from 92.72% to 90.89%) allows for a substantial increase in device autonomy (of 3.7x) while also facilitating faster detection (from 710 ms to 540 ms).

Experimental devices aiming at real-time detection and suppression of epileptic-seizure events in live subjects already exist. However, to guarantee high detection accuracy, existing approaches employ high-accuracy detection filters that overlook the incurred energy costs, thus leading to unrealistic solutions for low-power implementations. In this short paper, we capitalize on the approximate nature of the seizure-detection phenomenon and propose an energy-efficient scheme for embedded, seizure-detection devices with trivial impact on detection accuracy. For a 1% reduction in filter detection accuracy we achieve a 3.7x increase in device-battery lifetime.

The Inter-Pulse-Interval (IPI) of heart beats has previously been suggested for security in mobile health (mHealth) applications. In IPI-based security, secure communication is facilitated through a security key derived from the time difference between heart beats. However, there currently exists no work which considers the effect on security of imperfect heart-beat (peak) detection. This is a crucial aspect of IPI-based security and likely to happen in a real system. In this paper, we evaluate the effects of peak misdetection on the security performance of IPI-based security. It is shown that even with a high peak detection rate between 99.9% and 99.0%, a significant drop in security performance may be observed (between -70% and -303%) compared to having perfect peak detection. We show that authenticating using smaller keys yields both stronger keys as well as potentially faster authentication in case of imperfect heart beat detection. Finally, we present an algorithm which tolerates the effect of a single misdetected peak and increases the security performance by up to 155%.

Recent work on wireless Implantable Medical Devices (IMDs) has revealed the need for secure communication in order to prevent data theft and implant abuse by malicious attackers. However, security should not be provided at the cost of patient safety and an IMD should, thus, remain accessible during an emergency regardless of device security. In this paper, we present a novel method of providing IMD emergency access, based on generating Entity Identifiers (EI) using the Inter-Pulse Intervals (IPIs) of heartbeats. We evaluate the current state-of-the-art in EI-generation in terms of security and accessibility for healthy subjects with a wide range of heart rates. Subsequently, we present an adaptive EI-generation algorithm which takes the heart rate into account, maintaining an acceptable emergency-mode activation time (between 5-55.4 s) while improving security by up to 3.4x for high heart rates. Finally, we show that activating emergency mode may consume as little as 0.24μJ from the IMD battery.

Secure and energy-efficient communication between Implantable Medical Devices (IMDs) and authorized external users is attracting increasing attention these days. However, there currently exists no systematic approach to the problem, while solutions from neighboring fields, such as wireless sensor networks, are not directly transferable due to the peculiarities of the IMD domain. This work describes an original, efficient solution for secure IMD communication. A new implant system architecture is proposed, where security and main-implant functionality are made completely decoupled by running the tasks onto two separate cores. Wireless communication goes through a custom security ASIP, called SISC (Smart-Implant Security Core), which runs an energy-efficient security protocol. The security core is powered by RF-harvested energy until it performs external-reader authentication, providing an elegant defensemechanism against battery Denialof- Service (DoS) and other, more common attacks. The system has been evaluated based on a realistic case study involving an artificial pancreas implant. When synthesized for a UMC 90nm CMOS ASIC technology, our system architecture achieves defense against unauthorized accesses having zero energy cost, running entity authentication through harvesting only 7.45μJ of RF energy from the requesting entity. In all other successfully authenticated accesses, our architecture achieves secure data exchange without affecting the performance of the main IMD functionality, adding less than 1‰ (1.3mJ) to the daily energy consumption of a typical implant. Compared to a singe-core, secure reference IMD, which would still be more vulnerable to some types of attacks, our secure system on chip (SoC) achieves high security levels at 56% energy savings and at an area overhead of less than 15%.

In this paper, we describe the design and implementation of a new fault-tolerant RISC-processor architecture suitable for a design framework targeting biomedical implants. The design targets both soft and hard faults and is original in efficiently combining as well as enhancing classic fault-tolerance techniques. The proposed architecture allows run-time tradeoffs between performance and fault tolerance by means of instruction-level configurability. The system design is synthesized for UMC 90nm CMOS standard-process and is evaluated in terms of fault coverage, area, average power consumption, total energy consumption and performance for various duplication policies and test-sequence schedules. It is shown that area and power overheads of approximately 25% and 32%, respectively, are required to implement our techniques on the baseline processor. The major overheads of the proposed architecture are performance (up to 107%) and energy consumption (up to 157%). It is observed that the average power consumption is often reduced when a higher degree of fault tolerance is targeted. It is shown that test sequences can effectively be scheduled during the available program stalls and that nearly all soft faults are tolerated by using instruction duplication. The main advantages of the proposed architecture are the high portability of the introduced architecture-level fault-tolerance techniques, the flexibility in trading processor overheads for required fault-tolerance degree as well as affordable area and power consumption overheads.