Rv
R van Veldhoven
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3 records found
1
Master thesis
(2026)
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Fekry Mohamed, K.A.A. Makinwa, T.M. Lopes Marta da Costa, Robert van Veldhoven
This thesis presents a passive-input dual-loop continuous-time sigma–delta modulator that suppresses first-stage quantization noise in the analog domain. The proposed architecture requires only a fixed digital attenuation, avoiding a complex digital cancellation filter and dedicated calibration loop. Implemented in TSMC 65 nm CMOS, the modulator operates from a 1.2 V supply with a 100 MHz sampling frequency and an approximately 200 kHz signal bandwidth. Schematic-level simulations achieve a peak SNDR of 100.61 dB and a dynamic range of 103.66 dB while consuming 1.094 mW. RCC-extracted simulations achieve an SNR of 100 dB and an SNDR of 99.53 dB.
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This thesis presents a passive-input dual-loop continuous-time sigma–delta modulator that suppresses first-stage quantization noise in the analog domain. The proposed architecture requires only a fixed digital attenuation, avoiding a complex digital cancellation filter and dedicated calibration loop. Implemented in TSMC 65 nm CMOS, the modulator operates from a 1.2 V supply with a 100 MHz sampling frequency and an approximately 200 kHz signal bandwidth. Schematic-level simulations achieve a peak SNDR of 100.61 dB and a dynamic range of 103.66 dB while consuming 1.094 mW. RCC-extracted simulations achieve an SNR of 100 dB and an SNDR of 99.53 dB.
This thesis describes the design of a 3rd order 1-bit delta-sigma modulator whose input-signal range (0 to 1.95V) exceeds its supply voltage (1.2V). By using a passive input stage and a single-OTA resonator, this beyond-the-rails modulator realizes a 3rd order loop filter with only two amplifiers instead of the usual three and thus achieves state-of-the-art energy efficiency. Realized in a standard TSMC 65nm CMOS technology, the modulator achieves 99.24dB SNR, 99.2dB SNDR and 100dB DR in a bandwidth of 24kHz while consuming only 80μW. This translates into the highest energy efficiency (FoMSNDR, 184dB) reported for a continuous-time delta-sigma modulator.
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This thesis describes the design of a 3rd order 1-bit delta-sigma modulator whose input-signal range (0 to 1.95V) exceeds its supply voltage (1.2V). By using a passive input stage and a single-OTA resonator, this beyond-the-rails modulator realizes a 3rd order loop filter with only two amplifiers instead of the usual three and thus achieves state-of-the-art energy efficiency. Realized in a standard TSMC 65nm CMOS technology, the modulator achieves 99.24dB SNR, 99.2dB SNDR and 100dB DR in a bandwidth of 24kHz while consuming only 80μW. This translates into the highest energy efficiency (FoMSNDR, 184dB) reported for a continuous-time delta-sigma modulator.
Temperature threshold sensors facilitate temperature protection in microprocessors by indicating when the processor gets overheated or too cold. This thesis presents a BJT based temperature sensor with a programmable temperature threshold from -40°C to 150°C. Comparison of a CTAT voltage with a PTAT voltage gives a one-bit digital output when the temperature of the die exceeds the set threshold. This work achieves a temperature detection accuracy of ±0.75°C, leading to the lowest reported relative inaccuracy among temperature switches by using a room temperature digital trim and without the use of any dynamic techniques. The design has a current consumption of 7uA, and the estimated area of the system is less than 0.05mm2 in 0.16µm CMOS technology.
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Temperature threshold sensors facilitate temperature protection in microprocessors by indicating when the processor gets overheated or too cold. This thesis presents a BJT based temperature sensor with a programmable temperature threshold from -40°C to 150°C. Comparison of a CTAT voltage with a PTAT voltage gives a one-bit digital output when the temperature of the die exceeds the set threshold. This work achieves a temperature detection accuracy of ±0.75°C, leading to the lowest reported relative inaccuracy among temperature switches by using a room temperature digital trim and without the use of any dynamic techniques. The design has a current consumption of 7uA, and the estimated area of the system is less than 0.05mm2 in 0.16µm CMOS technology.