Hyperscalers Meta and Google have observed a rare but severe phenomenon in cores throughout their processor fleets: Silent Data Errors (SDEs). Recent research efforts have indicated that marginal timing failures are the main cause of these SDEs. Currently, the underlying defects causing these failures, systematically escape production testing like full scan tests. Moreover, ageing-related failures that develop over the lifetime of a chip can also cause SDEs. To ensure reliability and to detect marginal defects, in-field testing is crucial. A promising approach for in-field testing is Software-Based Self-Test (SBST). This allows for online testing of a core by running a software program that activates faults and observes test responses. These programs are based on structural test patterns created by constraining ATPG (CATPG) to functionally possible inputs. The resulting test patterns are then converted into instructions, and faults are propagated into data memory, to be observed. Therefore, SBST programs enable testing a processor core while it is in functional mode. Recent SBST works have shifted from the stuck-at fault (SAF) model to the transition delay fault (TDF) model. Static fault models, such as the SAF model, fall short in modelling the marginal timing failures that cause SDEs. However, SBST programs targeting TDFs provide less coverage than the structural production test approach full scan. This thesis proposes a methodology to increase fault coverage (FC) of SBST programs, targeting TDFs, with a low area Design-for-Test (DFT) hardware addition to a core.
Increasing the FC of structural tests can be achieved by improving the testability of a circuit. Improving the testability of a circuit requires enhancing either its observability or its controllability. The focus of this thesis is on increasing the observability of a core through the addition of DFT hardware. To add the DFT hardware to a core in a way that complements SBST, an SBST generation framework, an SBST simulation framework, and three DFT designs were developed. The frameworks use the proprietary ATPG tool Tessent by Siemens. The SBST generation framework is based on partial scan CATPG test patterns. A design space exploration, to justify the DFT additions, is done by tweaking the partial scan configuration used by the constrained ATPG. The SBST program and the DFT are tested by the simulation framework, which converts the software program into a test pattern file. This test pattern file is then simulated in Tessent, providing FC results. The exploration of the design space follows a methodology that is based on the capabilities of the ATPG tool. The SBST program FC is increased by enhancing the observability of a selection of flip-flops using DFT.
Two DFT designs are implemented. One in the control and status registers (CSR) module, and another in the instruction decode (ID) stage module. Results are provided for both DFT designs. The DFT in the CSR module achieved a FC increase of 6.29 percentage points for SAF and 2.40 percentage points for TDF, at a cost of 0.84% area overhead. Furthermore, the DFT in the ID stage module achieved a FC increase of 1.01 percentage points for SAF and 1.92 percentage points for TDF, for a 0.65% area overhead. It is also observed that increased observability is more essential for detection of TDFs than the detection of SAFs. The SAF coverage is higher than some other works, but the SBST program size is significantly larger. When comparing the TDF coverage to other works it is clear that the FC results are significantly lower. However, when comparing the DFT area overhead to other works it is shown that the DFT additions introduce relatively little area overhead. In conclusion, this thesis has shown that DFT hardware that complements SBST can increase SBST program FC for a small area overhead. This indicates that DFT could aid SBST programs in matching the FC achieved by full scan. That would make SBST complemented by DFT an alternative to full scan, with a lower area overhead and flexible in-field testing capabilities.
To improve the results of this work, future work should be done to improve the baseline SBST TDF FC. This could be done by introducing a feedback loop from fault simulation to the constrained ATPG. This would allow proving that the same FC increase for area overhead trade-off can be made with a baseline SBST program that has higher FC. Furthermore, no efforts were done to minimize SBST program size. So, there is improvement that can be done in this area. The main limitations of this work are the justification step in the SBST pattern conversion and the functional constraint extraction process, resulting in lower fault coverage than that of state-of-the-art SBST works.
