High Volume Electrical Characterization of Semiconductor Qubits
R. Pillarisetty (Intel Corporation)
H.C. George (Intel Corporation)
Tom Watson (Intel Corporation)
L. Lampert (Intel Corporation)
Tobias Krähenmann (TU Delft - QCD/Vandersypen Lab, Intel Corporation, Kavli institute of nanoscience Delft, TU Delft - QuTech Advanced Research Centre)
A. M. Zwerver (Intel Corporation, Kavli institute of nanoscience Delft, TU Delft - QuTech Advanced Research Centre, TU Delft - QCD/Vandersypen Lab)
M. Veldhorst (Kavli institute of nanoscience Delft, TU Delft - QCD/Veldhorst Lab, TU Delft - QuTech Advanced Research Centre, Intel Corporation)
G. Scappucci (Kavli institute of nanoscience Delft, TU Delft - QuTech Advanced Research Centre, Intel Corporation, TU Delft - QCD/Scappucci Lab)
L. M.K. Vandersypen (Intel Corporation, Kavli institute of nanoscience Delft, TU Delft - QN/Vandersypen Lab, TU Delft - QuTech Advanced Research Centre, TU Delft - QCD/Vandersypen Lab)
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Abstract
Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.