High Volume Electrical Characterization of Semiconductor Qubits
R. Pillarisetty (Intel Labs)
H.C. George (Intel Labs)
Tom Watson (Intel Labs)
L. Lampert (Intel Labs)
T.S. Krähenmann (TU Delft - QCD/Vandersypen Lab, TU Delft - QuTech Advanced Research Centre, Kavli institute of nanoscience Delft, Intel Labs)
A.M.J. Zwerver (TU Delft - QuTech Advanced Research Centre, TU Delft - QCD/Vandersypen Lab, Intel Labs, Kavli institute of nanoscience Delft)
M. Veldhorst (Intel Labs, Kavli institute of nanoscience Delft, TU Delft - QCD/Veldhorst Lab, TU Delft - QuTech Advanced Research Centre)
Giordano Scappucci (Intel Labs, TU Delft - QCD/Scappucci Lab, TU Delft - QuTech Advanced Research Centre, Kavli institute of nanoscience Delft)
LMK Vandersypen (TU Delft - QCD/Vandersypen Lab, Intel Labs, TU Delft - QN/Vandersypen Lab, TU Delft - QuTech Advanced Research Centre, Kavli institute of nanoscience Delft)
G.B. More Authors (External organisation)
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Abstract
Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.