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On-chip output stage design for a continuous class-F power amplifier

Conference Paper (2021)
Author(s)

Anil Kumar Kumaran (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Masoud Pashaeifar (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Marco D'Avino (Catena)

Leo C.N. de Vreede (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Morteza S. Alavi (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Electronics
DOI related publication
https://doi.org/10.1109/ISCAS51556.2021.9401788 Final published version
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Publication Year
2021
Language
English
Research Group
Electronics
Article number
9401788
ISBN (electronic)
978-1-7281-9201-7
Event
53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 (2021-05-22 - 2021-05-28), Virtual at Daegu, Korea, Republic of
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Abstract

Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.

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