A quantum dot crossbar with sublinear scaling of interconnects at cryogenic temperature
P. L. Bavdaz (TU Delft - QCD/Scappucci Lab, Kavli institute of nanoscience Delft, TU Delft - QuTech Advanced Research Centre)
H. G.J. Eenink (Kavli institute of nanoscience Delft, TU Delft - BUS/Quantum Delft, TU Delft - QuTech Advanced Research Centre)
J. van Staveren (TU Delft - QuTech Advanced Research Centre, Kavli institute of nanoscience Delft, TU Delft - QCD/Sebastiano Lab)
M. Lodari (Kavli institute of nanoscience Delft, TU Delft - QCD/Scappucci Lab, TU Delft - QuTech Advanced Research Centre)
C. G. Almudever (Technical University of Valencia)
J. S. Clarke (Intel Corporation)
F. Sebasatiano (Kavli institute of nanoscience Delft, TU Delft - QuTech Advanced Research Centre, TU Delft - Quantum Circuit Architectures and Technology)
M. Veldhorst (Kavli institute of nanoscience Delft, TU Delft - QuTech Advanced Research Centre, TU Delft - QN/Veldhorst Lab)
G. Scappucci (TU Delft - QuTech Advanced Research Centre, TU Delft - QCD/Scappucci Lab, Kavli institute of nanoscience Delft)
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Abstract
We demonstrate a 36 × 36 gate electrode crossbar that supports 648 narrow-channel field effect transistors (FET) for gate-defined quantum dots, with a quadratic increase in quantum dot count upon a linear increase in control lines. The crossbar is fabricated on an industrial 28Si-MOS stack and shows 100% FET yield at cryogenic temperature. We observe a decreasing threshold voltage for wider channel devices and obtain a normal distribution of pinch-off voltages for nominally identical tunnel barriers probed over 1296 gate crossings. Macroscopically across the crossbar, we measure an average pinch-off of 1.17 V with a standard deviation of 46.8 mV, while local differences within each unit cell indicate a standard deviation of 23.1 mV. These disorder potential landscape variations translate to 1.2 and 0.6 times the measured quantum dot charging energy, respectively. Such metrics provide means for material and device optimization and serve as guidelines in the design of large-scale architectures for fault-tolerant semiconductor-based quantum computing.