Systematic Analysis of Interconnect and Contact Defects in RRAMs

Abstract

Resistive Random Access Memory (RRAM) has emerged as a promising candidate to succeed conventional memory technologies, offering advantages such as low energy operation and scalable storage density. As different manufacturers continue to advance RRAM toward large-scale production and commercial deployment, the demand for accurate and efficient testing methodologies becomes increasingly critical. This paper investigates interconnect and contact defects in RRAM arrays, with particular attention to the influence of the Data Background (DB), and proposes corresponding test strategies. A comprehensive defect space covering interconnect and contact defects is formulated for a layout-independent RRAM design. Systematic defect injection and circuit-level simulations are conducted to derive fault models, encompassing not only single-cell and two-cell coupling faults but also multi-cell faults strongly affected by DBs. The analysis identifies previously unreported 3-cell and 4-cell faults, which originate from defect-related sneak paths in the array. Conventional RRAM test schemes are unable to detect such faults. To address this limitation, a DB-aware test generation scheme is presented, capable of efficiently identifying all the aforementioned fault types and thereby enhancing the overall fault and defect coverage in RRAM devices.