DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Conference paper (2019)

Authors

G. Cardoso Medeiros Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
M. Fieback Computer Engineering - EEMCS
L. M. Bolzani Poehls Pontifical Catholic University of Rio Grande do Sul
S. Hamdioui Quantum & Computer Engineering
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2019 G. Cardoso Medeiros, M. Taouil, M. Fieback, L. M. Bolzani Poehls, S. Hamdioui
DOI
help_outline
https://doi.org/10.1109/ETS.2019.8791517
DFT SRAM FinFET Hard-to-Detect Faults
More Info
expand_more

Published Date

2019

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.