Device-Aware Test: A New Test Approach Towards DPPB Level
Moritz Fieback (TU Delft - Computer Engineering)
Lizhou Wu (TU Delft - Computer Engineering)
G. Cardoso Medeiros (TU Delft - Computer Engineering)
H. Aziza (Centre national de la recherche scientifique (CNRS))
S Rao (IMEC)
Erik Jan Marinissen (IMEC)
Mottagiallah Taouil (CognitiveIC, TU Delft - Computer Engineering)
Said Hamdioui (TU Delft - Quantum & Computer Engineering, CognitiveIC)
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Abstract
This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach suggests), but it rather incorporates the impact of the physical defect on the technology parameters of the device and thereafter on its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis (based on fault simulation) is performed to derive appropriate fault models and subsequently test solutions. The approach is demonstrated using two memory technologies: resistive random access memory (RRAM) and spin-transfer torque magnetic random access memory (STT-MRAM). The results show that the proposed approach is able to sensitize faults for defects that are not detected with the traditional approach, meaning that the latter cannot lead to high-quality test solutions as required for a defective part per billion (DPPB) level. The new approach clearly sets up a turning point in testing for at least the considered two emerging memory technologies.