This paper describes the microfabrication and electrical characterization of aluminum-coated superconducting through-silicon vias (TSVs) with sharp superconducting transition above 1 K. The sharp superconducting transition was achieved by means of fully conformal and void-free DC-sputtering of the TSVs with Al, and is here demonstrated in up to 500μ m-deep vias. Full conformality of Al sputtering was made possible by shaping the vias with a tailored hourglass profile, which allowed a metallic layer as thick as 430 nm to be deposited in the center of the vias. Single-via electric resistance as low as 160 mΩ at room temperature and superconductivity at 1.27 K were measured by a three-dimensional (3D) cross-bridge Kelvin resistor structure. This work establishes a CMOS-compatible fabrication process suitable for arrays of superconducting TSVs and 3D integration of superconducting silicon-based devices. [2020-0354].@en

This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of 300 μm-deep and 50 μmwide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall profile for the axisymmetric vias. Single-via electric resistance as low as 80.44 mΩ at room temperature and superconductivity below 1.28 K were measured by a crossbridge Kelvin resistor structure. This work thus demonstrates the fabrication of functional superconducting interposer layers, suitable for high-density 3D integration of silicon-based quantum computing architectures.@en

We describe a microfabrication process that, thanks to a specifically tailored sidewall profile, enables for the first-time wafer-scale arrays of high-aspect ratio through-silicon vias (TSVs) coated with DC-sputtered Aluminum, achieving at once superconducting and CMOS-compatible 3D interconnects. Void-free conformal coating of up to 500μm-deep and 50μm-wide vias with a mere 2μm-thick layer of Al, a widely available metal in for IC manufacturing, was demonstrated. Single-via electric resistance as low as 468 mΩ at room temperature and superconductivity at 1.25 K were measured by a cross-bridge Kelvin resistor structure. This work establishes the fabrication of functional superconducting interposers suitable for 3D integration of high-density silicon-based quantum computing architectures.@en

System downscaling, 3D integration, and increasing functionalities are the main challenges that integrated circuits and MEMS technology have dealt with in the past decade. Advanced packaging schemes and interconnect technologies are some of the successful approaches to tackle the challenges. These issues also extend to modern designs such as terahertz applications and quantum technologies, particularly the solid-state quantum computer. In-demand instances of the latter are e.g. high-density quantum computing systems, where the layer implementing quantum bits (qubits) needs to be bridged to the microelectronic control layer. The latter typically requires CMOS-based circuitry compatible with cryogenic temperatures (i.e., cryo-CMOS) for the control and readout of the many physical qubits needed to implement error-tolerant logical qubits. In order to scale the number of qubits, a more efficient way for the interconnection of the qubits is necessary. In line with such a three-dimensional (3D) integration approach, an interposed layer featuring superconducting vertical interconnections such as through-silicon vias (TSVs) represents a crucial element in the fabrication and assembly of large, scalable, and densely integrated superconducting systems....@en