In this paper, the interference mitigation for Frequency Modulated Continuous Wave (FMCW) radar system with a dechirping receiver is investigated. After dechirping operation, the scattered signals from targets result in beat signals, i.e., the sum of complex exponentials while the interferences lead to chirp-like short pulses. Taking advantage of these different time and frequency features between the useful signals and the interferences, the interference mitigation is formulated as an optimization problem: a sparse and low-rank decomposition of a Hankel matrix constructed by lifting the measurements. Then, an iterative optimization algorithm is proposed to tackle it by exploiting the Alternating Direction of Multipliers (ADMM) scheme. Compared to the existing methods, the proposed approach does not need to detect the interference and also improves the estimation accuracy of the separated useful signals. Both numerical simulations with point-like targets and experiment results with distributed targets (i.e., raindrops) are presented to demonstrate and verify its performance. The results show that the proposed approach is generally applicable for interference mitigation in both stationary and moving target scenarios.

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A novel matrix-pencil (MP)-based interference mitigation approach for frequency-modulated continuous-wave (FMCW) radars is proposed in this article. The interference-contaminated segment of the beat signal is first cut out, and then, the signal samples in the cutout region are reconstructed by modeling the beat signal as a sum of complex exponentials and using the MP method to estimate their parameters. The efficiency of the proposed approach for the interference with different parameters (i.e., interference duration, signal-to-noise ratio (SNR), and different target scenarios) is investigated by means of numerical simulations. The proposed interference mitigation approach is intensively verified on experimental data. Comparisons of the proposed approach with the zeroing and other beat-frequency interpolation techniques are presented. The results indicate the broad applicability and superiority of the proposed approach, especially in low SNR and long interference duration situations.

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This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased Σ Δ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of Σ Δ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply).

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A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm 2 ). Most circuitry operates at 32× lower frequency than the DCO in order to reduce the total power consumption down to 181 nW. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of ΣΔ modulation to improve the DCO resolution. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle at 417 kHz) over prior art while keeping excellent on-par long-term stability (Allan deviation floor <;20 ppm) and temperature stability (106 ppm/°C).@en

Simultaneous measurement of Electrocardiogram (ECG) and bio-impedance (BioZ) via disposable health patches is desired for patients suffering from chronic cardiovascular and respiratory diseases. However, a sensing IC must consume ultra-low power under a sub-volt supply to comply with miniaturized and disposable batteries. This work presents a 0.6 V analog frontend (AFE) IC consisting of an instrumentation amplifier (IA), a current source (CS) and a SAR ADC. The AFE can measure ECG and BioZ simultaneously with a single IA by employing an orthogonal chopping scheme. To ensure the IA can tolerate up to 300mVpp DC electrode offset and 400mV pp common-mode (CM) interference, a DC-servo loop (DSL) combined with a common-mode feedforward (CMFF) loop is employed. A buffer-assisted scheme boosts the IA's input impedance by 7x to 140MΩ at 10Hz. To improve the BioZ sensitivity, the CG utilizes dynamic element matching to reduce the 1/f noise of the output current, leading to 35mΩ/√Hz BioZ sensitivity down to 1Hz. The ADC shows a 9.7b ENOB when sampled at 20ksps. The total power consumption of the AFE is 3.8μW. @en