We present a detailed material study of n⁺-type polysilicon (polySi) and its application as a carrier selective rear contact in a bifacial n-type solar cell comprising fire-through screen-printed metallization and 6" Cz wafers. The cells were manufactured with low-cost industrial process steps yielding V_ocs from 676 to 683 mV and J_scs above 39.4 mA/cm² indicating an efficiency potential of 22%. The aim of this study is to understand which material properties determine the performance of POCl₃-diffused (n-type) polySi-based passivating contacts and to find routes to improve its use for industrial PERPoly (Passivated Emitter Rear PolySi) cells from the point of view of throughput, performance, and bifacial application. This paper reports on correlations between the parameters used for low pressure chemical vapour deposition (LPCVD), annealing, and doping on optical, structural, and electronic properties of the polySi-based passivating contact and the subsequent influence on the solar cell parameters.

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.