With the rapid advancement of power semiconductor packaging technologies, Smart P2 Packagingaging has emerged as a pivotal innovation for enhancing system performance and miniaturization. This study systematically investigates the thermal conduction characteristics and stress distributions of copper-filled vias (CFVs) in Smart P2Pack frontal interconnects through coupled thermal-mechanical finite element analysis. Results indicate that increasing CFV diameter enhances vertical heat conduction but causes localized heat accumulation and stress concentration due to the low thermal conductivity of encapsulation materials, elevating interfacial failure risks. Conversely, expanding CFV pitch promotes dispersed heat flow and reduces chip temperature but concurrently lowers local structural stiffness and exacerbates stress concentration. Optimal CFV design thus requires balancing thermal diffusion performance and mechanical constraints to ensure structural reliability and thermal stability.