A modular approach to high-precision current amplifiers benefits lithography machines by reducing size and increasing efficiency. This research proposes two promising controller structures for a modular topology: a parallel controller structure and a cascaded controller structure. The study evaluates and compares their performance, introduces Delta-Sigma (DS) Analog-to-Digital Converters (ADCs) as a cost-effective alternative, and investigates their limitations in the proposed controller structures. A Feed Forward (FF) strategy is introduced to enhance the frequency response performance of both controllers.
Two methods to increase efficiency, particularly in amplifiers that are using interleaved Pulse-Width Modulation (PWM), are introduced: Phase-Shedding (PS) and Zero-Voltage Switching (ZVS). By estimating power losses it is shown that PS increases power efficiency for lower current setpoints, while ZVS increases efficiency for higher current setpoints. The study investigates how these methods impact controller stability and output current performance.
A hardware implementation validates the operation of the two controller structures. Stability issues with the cascaded controller structure become apparent and are resolved by a method that sacrifices bandwidth. Various measurements are conducted, and their results are compared to analytical expectations. The best frequency response is obtained using the parallel controller structure with a complex FF strategy, which gives a magnitude response of -0.3 dB and a phase shift of -3.6° at a 400 Hz setpoint.
When comparing the two controller structures, each has its own advantages and disadvantages. Choosing between the structures should be based on specific application requirements. If the application requires large bandwidth with high stability, the parallel controller should be selected. If the application requires good modularity, low quantization noise, and disturbance rejection performance, the cascaded controller should be selected.

This thesis will discuss the design, simulations and measurements of a powerline communication system that utilizes FSK modulation in order to transfer information from a transmitter to a receiver at a baud rate of 1kbps, in order to reach the requirement of having an effective data rate of at least 6bps. This system is designed specifically to be implemented in the smart DC grid of a sustainable "tiny house" community. This thesis investigates the different subsystems needed to create this communication system and compares different methods and implementations. This research led to the conclusion that the communication system was successfully build and could reliably reach a baud rate of 700bps, which appeared to be more than enough to reach a data rate of 6bps. The system also showed to be resistant to 'high levels' of noise on the communication channel as defined in the CELENEC standard. Furthermore, in order to decrease the bit error rate further, additional bit error detection and correction has been implemented using microcontrollers. This led to a robust and nearly error free communication system over a tested powerline of 50 meters long.