Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other hand, is a fundamentally nonlinear circuit element, thus susceptible to benefit from SR, which recently came in the spotlight of the emerging technologies potential candidates. However, at this time, the variability exhibited by manufactured memristor devices within the same array constitutes the main hurdle in the road towards the commercialisation of memristor-based memories and/or computing units. Thus, in this paper, memristor SR effects are explored, assuming various memristor models, and SR-based memristance range enhancement, tolerant to device-to-device variability, is demonstrated. Our experiments reveal that SR can induce significant RMAX/RMIN ratio increase under up to 60% variability, getting as high as 3.4× for 29 dBm noise power.

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Memristors are considered a promising emerging device that may improve some specific applications, like memories, or make feasible new ones, mainly alternative computing architectures. However, it is not a mature technology and their characteristics can vary significantly depending on their structures. Also, variability and reliability might suppose an important issue in some applications. In this paper, a chalcogenide memristor is studied and their main parameters are extracted. Then, it's discused how their properties can affect two applications: a memory circuit and a digital computing alternative, the logic implication technique.@en

Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and consequent orientation to low power consumption. Advances in the RRAM technology as well as enhancement of the control of the cells are opening the use of these devices for multi-valued logic. But the cycle-to-cycle variability and the still reduced endurance are becoming serious limitations. This paper analyzes the impact of both mechanisms on 1T1R cells and suggests potential adaptive mechanisms to enlarge its lifetime.@en

The need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention due to their attractive characteristics such as scalability and CMOS friendly manufacturing. However, similar to any other new technology emergences, having reliability and high performance devices is a challenge, and innovative new techniques are required to make the products attractive and robust enough before entering into the semiconductor market. The research for such crucial reliability concerns and mitigation techniques are ongoing hot topic and the main motivation for this work. Therefore, in this paper, we have studied the origins of RRAM variability and reviewed some of the existing techniques to mitigate its effect at circuit level. To show the relevance of variability in RRAM memories we have further analyzed its impact in the Read/Write memory operation and have presented the memory unreliability that we measure by a parameter as probability of error can be 25% during the read operation and in presence of such resistance variations. In the next phase we have presented a conventional 1T1R memory architecture where we have proposed our reconfiguring strategies to extend the memory lifetime. These reconfiguration strategies utilize a monitoring technique, what we have implemented in order to measure the resistance ratios in RRAM memory cells. Such monitoring approach can detect the highly variability effected and differentiate the bad cells from the good cells; therefore, it can improve the overall RRAM memory reliability.@en

Emerging technologies such as RRAMs are attracting significant attention, due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures (such as process variation due to their nano-scale structure) have gained considerable importance for having acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit and system level. In this paper we have first reviewed the RRAM variability phenomenon and the variation tolerant techniques at the circuit level. Then we have analyzed the impact of variability on memory reliability and have proposed a variation-monitoring circuit that discerns the reliable memory cells affected by process variability.@en