Miniaturization of next-generation active neural implants requires novel micro-packaging solutions that can maintain their long-term coating performance in the body. This work presents two thin-film coatings and evaluates their biostability and in vivo performance over a 7-month animal study. To evaluate the coatings on representative surfaces, two silicon microchips with different surface microtopography are used. Microchips are coated with either a ≈100 nm thick inorganic hafnium-based multilayer deposited via atomic layer deposition (ALD-ML), or a ≈6 µm thick hybrid organic–inorganic Parylene C and titanium-based ALD multilayer stack (ParC-ALD-ML). After 7 months of direct exposure to the body environment, the multilayer coatings are evaluated using optical and cross-sectional scanning electron microscopy. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) is also used to evaluate the chemical stability and barrier performance of the layers after long-term exposure to body media. Results showed the excellent biostability of the 100 nm ALD-ML coating with no ionic penetration within the layer. For the ParC-ALD-ML, concurrent surface degradation and ion ingress are detected within the top ≈70 nm of the outer Parylene C layer. The results and evaluation techniques presented here can enable future material selection, packaging, and analysis, enhancing the functional stability of future chip-embedded neural implants.

To meet the dimensional requirements for bioelectronic medicine, new packaging solutions are needed that could enable small, light-weight and flexible implants. For protecting the implantable electronics against biofluids, recently various atomic layer deposited (ALD) coatings have been proposed with high barrier properties. Before implantation, however, the protective coating should be evaluated for any defects which could otherwise lead to leakage and device failure. In these cases, the conventional helium leak test method can no longer be used due to the millimeter size of the implant. Therefore, an in-situ sensing platform is needed that could evaluate the coating and justify the implantation of the final device. In this work, we explore the possibility of using the CMOS bulk for such a platform. Towards this aim, as a proof of concept, test chips were made in a standard 6-metal 0.18 μm CMOS process and for the connection to the bulk, a p+ diffusion was used. A group of samples was then coated with an ALD multilayer. For coating evaluation, off-chip DC current leakage and impedance measurements were carried out in saline between the CMOS bulk and a platinum reference electrode. Results were compared between non-coated and coated chips that clearly demonstrated the potential of using the bulk as a sensing platform for coating evaluations. This novel approach could pave the way towards an all integrated in-situ hermeticity test, currently missing in mm-size implants.