Ultrasound (US) neuromodulation is a widely-used technique in the field of neuroscience and medical therapy that uses ultrasound waves to non-invasively modulate neural activity. The miniaturization of modern ultrasonic systems has an intimate relation with system power consumption. As the advancement of Integrated Circuits (ICs) represents a powerful stride in achieving the compactness and integration of ultrasound systems, power efficiency is always a challenge in ICs. The pulser is a power-consuming part in the transmitter stage, because a considerable power should be used to charge and discharge the parasitic capacitor of the US transducer. This project aims to design a power-efficient pulser for an ultrasound transducer, which is adopted in a 2D ultrasound phased-array transmitter (TX). The area of the TX circuit in a 2D phased array is limited to half of the sound wavelength, requiring an area limitation for the circuit. The transducer element used in this case has an area of 100*100 um^2. Thus, the area occupation is also considered as an important aspect through the design process. This work designs a power-efficient 3-level high-voltage pulser with TSMC 180-nm BCD Technology. The proposed pulser interfaces an ultrasound PZT transducer with a resonant frequency of 8.15 MHz. A bootstrap structure is utilized in this design to double the 10-V supply voltage. Five switches are controlled open and close to determine the voltage level at the output node, where three control signals are needed. The design adopts stacked standard CMOS transistors instead of HV transistors for the switches. As the transistors inevitably act as one of the power-hungry parts in the circuit, a smart design of shortly close one of the switches is proposed to save more energy. The 3 levels of the output voltage level from the proposed pulser are near 0, 8 V and 15 V. Thus, as a reference for comparison, a conventional class-D pulser with a supply voltage of 15 V is also presented. It is worth mentioning that to make the comparison as fair as possible, the conventional pulser is also designed in its most power-efficient condition. The simulation result shows a 35.4% power efficiency enhancement of the proposed design compared with the conventional class-D pulser.