A. Urso
Please Note
9 records found
1
Bidirectional Bioelectronic Interfaces: System Design and Circuit Implications
System Design and Circuit Implications
This paper presents a novel multichannel level-crossing (MLC) ADC architecture aimed at recording atrial electrograms from multiple channels. The proposed architecture combines synchronous sampling with level-crossing (LC) quantisation to achieve activity dependent operation while recording from multiple channels simultaneously. In the proposed architecture the number of comparisons performed by the quantiser to reach a decision is dependent on the activity of the input signal and is 2-3.3 times lower than that in a conventional SAR ADC. The architecture uses one comparator and one reference level instead of two comparators and two reference levels as in conventional LC ADCs. The proposed architecture is modeled in VerilogA and is designed to be implemented in a standard 0.18 um CMOS process. The MLC ADC converts signals from 4 channels simultaneously and achieves an SFDR of 53.33 dB and an SNDR of 48.96 dB while consuming 9.32 μW of power from a 1.8 V power supply.
In order to recruit neurons in excitable tissue, constant current neural stimulators are commonly used. Recently, ultra high-frequency (UHF) stimulation has been proposed and proven to have the same efficacy as constant-current stimulation. UHF stimulation uses a fundamentally different way of activating the tissue: each stimulation phase is made of a burst of current pulses with adjustable amplitude injected into the tissue at a high (e.g., 1 MHz) frequency. This paper presents the design, integrated circuit (IC) implementation, and measurement results of a power efficient multichannel UHF neural stimulator. The core of the neurostimulator is based on our previously proposed architecture of an inductor-based buck-boost dc-dc converter without the external output capacitor. The ultimate goal of this work is to increase the power efficiency of the UHF stimulator for multiple-channel operation, while keeping the number of external components minimal. To this end, a number of novel approaches were employed in the integrated circuit design domain. More specifically, a novel zero-current detection scheme is proposed. It allows to remove the freewheel diode typically used in dc-dc converters to prevent current to flow back from the load to the inductor. Furthermore, a gate-driver circuit is implemented which allows the use of thin gate-oxide transistors as high-voltage switches. By doing so, and exploiting the fundamental working principle of the proposed current-controlled UHF stimulator, the need for a high-voltage supply is eliminated and the stimulator is powered up from a 3.5 V input voltage. Both the current detection technique and the gate driving circuit of the current implementation allow to boost the power efficiency up to 300% when compared to previous UHF stimulator works. A peak power efficiency of 68% is achieved, while 8 independent channels with 16 fully configurable electrodes are used. The circuit is implemented in a 0.18 μm HV process, and the total chip area is 3.65 mm2
Comments on "Compact, Energy-Efficient High-Frequency Switched Capacitor Neural Stimulator With Active Charge Balancing" (vol 11, pg 878, 2017)
Comments on 'Compact, energy-efficient high-frequency switched capacitor neural stimulator with active charge balancing (IEEE Transactions on Biomedical Circuits and Systems (2017) 11:4 (878–888) DOI: 10.1109/TBCAS.2017.2694144)
This manuscript points out some mistakes in the Introduction and in the table of comparison of a paper already published in this journal by Hsu and Schmid [1]. Although the main claim of [1] is still preserved, we believe the paper needs to be rectified for scientific correctness of the work. In [1], the first High Frequency Switched-Capacitor (HFSC) stimulator is presented. The stimulation voltage is derived from the main supply by using an 1 : 1 switched-capacitor DC-DC converter. This particular topology of DC-DC converter operates as a resistor [2]. The further away the output voltage is from the input voltage, the lower the power efficiency is. As a result, the output voltage of the DC-DC converter, and therefore the total charge delivered to the tissue, can only be regulated at the expense of the power efficiency. Section I of [1], provides an overview of the most recently published works in the field of electrical stimulation. Based on the stimulation mode, Hsu and Schmid classify the papers into three categories, named voltage-mode stimulation (VMS), current-mode stimulation (CMS) and switched-capacitor stimulation (SCS). In [1], thework presented in [3] has been classified as SCS.However, [3] proposes CMS which adapts the voltage supply of the neurostimulator to the voltage across the electrodes. In [1], the work presented in [4] has been classified as VMS. However, [4] proposes a CMS. In fact, an inductor-based DC-DC converter without the output capacitance is used to deliver the charge to the tissue. Section V of [1] provides a table of comparison, in which the performances of the stimulator circuit are compared with some relevant contributions found in literature. Several errors have been found in the comparison table. The entries in bold characters and red colour of Table I below corrects the table of comparison presented in [1]. II. CONCLUSION The aim of this comment is two-fold. Firstly, it corrects a classification of the most recent works, which was presented in the Introduction of a paper previously published in this journal [1]. Secondly, it corrects some mistakes in its table of comparison. Although errors have been found, the main claim of [1], and hence its scientific contribution, are still preserved. [Table Presented].
A novel gate-driver technique for the switches involved in the conversion is proposed. It ensures an optimal overdrive voltage of the transistor, irrespective of its source and drain potentials. The 16-phase interleaved converter employs a charge recycling technique and uses a total on-chip capacitance of 3 nF.
The RSC converter is designed to be implemented in a standard 40 nm CMOS process which offers a capacitor density of approximately 2 nF/mm^2. Circuit simulations over the whole input voltage range show a power efficiency never lower than 54 % with a peak value of 92.7 %. ...
A novel gate-driver technique for the switches involved in the conversion is proposed. It ensures an optimal overdrive voltage of the transistor, irrespective of its source and drain potentials. The 16-phase interleaved converter employs a charge recycling technique and uses a total on-chip capacitance of 3 nF.
The RSC converter is designed to be implemented in a standard 40 nm CMOS process which offers a capacitor density of approximately 2 nF/mm^2. Circuit simulations over the whole input voltage range show a power efficiency never lower than 54 % with a peak value of 92.7 %.